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TMDSEVM6657LS using SPI with chip select 0 issue

SGQ
Expert 2875 points
Other Parts Discussed in Thread: TMDSEVM6657

Hi,

I am testing with TMDSEVM6657LS' SPI, and successful in using CS1.  Since SPI CS1 is used for FPGA configuration, I am switching to use CS0.  Does not matter how I setup the SPI, I am not able to see any CS0 line move on o-scope. 

But if I change dip switches to SPI boot,  I can see SPI access with CS0 on o-scope.

Thank you.

Regards,

Steve

Here are my SPI register values:

20bf0000 00000001 01000003 00000000 00000000

20bf0010 01000200 01010E01 00000000 00000102

20bf0020 00000000 00000000 00000000 00000000

20bf0030 01010F03 00000000 00000000 10020000

20bf0040 80000000 80000000 08080000 00000001

20bf0050 00010F08 00000000 00000000 00000000

20bf0060 00000000 00000000 00000000 00000000  

  • 0
    TI__Guru** 116170 points

    SGQ,

    I am not sure I completely understand the question but in SPI boot mode the BOOT ROM probes the boot switches to populate the SPI boot parameter table. Chip select is one of the fields that can be specified from the boot switches and the value gets latched to the BOOTMODE[12:0] field in the DEVSTAT register. Please look  at the definition of the BOOTMODE field in the C6657 device data sheet for more details regarding this configuration.

    Regards,

    Rahul

  • 0
    Prodigy 20 points
    Hi SGQ,

    I am reading your post, and i think your could help me.

    I have a problem with SPI driver with C6657 DSP.

    I am working with evaluation board "TMDSEVM6657". In this board, the CS1 allows communicate with a FPGA.

    My problem is that i can't program the CS1. I have read many times the TI User Guide. And i think i have understood how to configure SPIPC0, SPIDAT1 and SPIDEF registers for CS fields.

    After running, i have the interrupt error 0x11 in INTVEC0 (which is : Error interrupt pending). I can append when the rate is too high. I changed the frequency but nothing changes.

    So, i took my oscilloscope to observe SPI signal (CLK, CS, MOSI, MISO). I see that CLK signal looks good, but the CS signal stays in high level ( it never goes to lew level).

    I have seen in your post that you write SPI registers when you choose CS0. And you said you can test CS1 and it's work.

    Could you print me your SPI registers after configuration CS1 and just before running SPI com'.

    Thanks
  • 0 in reply to Martin Dupond
    Intellectual 290 points
    Hi SGQ and Martin,
    Can you please share your CCS projects for DSP to FPGA communication over SPI?
    I am having problems in this.

    Thanks & BRs,
    Hemraj
  • 0 in reply to Hemraj Kumhar
    Expert 2875 points

    Hi Hemraj,

    Sorry that I cannot share my code due to company policy.

    Regards,

    Steve

  • 0 in reply to SGQ
    Intellectual 290 points
    Dear SGQ,
    Can you please share your SPI registers after configuring CS1 and just before running SPI transfer?
    Any help in this regard will be highly appreciated.

    Thanks & BRs,
    Hemraj