• State
  • Locked Locked
  • Replies 3 replies
  • Subscribers 98 subscribers
  • Views 857 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

SN65DSI85 controller operation in two single-link mode with OMAP5

Hardik Patel2
Prodigy 30 points
Other Parts Discussed in Thread: SN65DSI85, SN65DSI83

Hi,

We are trying to use SN65DSI85(DSI to LVDS) controller with OMAP5.

OMAP's DSI1_A and DSI1_C are respectively connected to DSIA and DSIB inputs of SN controller.
And, LVDSB output of SN controller is connected to LCD. LVDSA output of SN has kept unconnected.

I would like to mention couple of things we learn from SN controller's datasheet:
1) SN controller's PLL gets locked by DSIA input's clock.
2) SN controller doesn't have any single-link mode that goes from DSIA to LVDSB.

- So, As we want full output on LVDSB, we are using SN controller's two singled like mode(DSIA -> LVDSA & DSIB -> LVDSB at a time).
- We are not using DIS1_A for any data transfer. Only DSI1_A's clock will be used as needed by SN to lock PLL.
- We are transferring framebuffer output over DSI1_C -> DSIB of SN -> LVDSB of SN -> LCD. However, we are not seeing anything on LG and we are getting CHA_LLP_ERR bit error in CSR 0xE5 and 0xE6.

How SN will behave in two single-link mode, if DISA line is not used for data transfer? Will it impact communication of B channel (DSI1_C -> DSIB of SN -> LVDSB of SN -> LCD) or operation of SN itself?

Thanks,
Hardik

  • 0
    TI__Mastermind 29520 points

    Hello Hardik,

    I familiarized with your question and checked for information.

    I found the following requirement for unused DSI Channels or Lanes of SN.
    - Unused DSI input terminals (DA*N/P, DB*N/P) of SN should be left unconnected or driven to LP11 state. (LP11 is state from MIPI specification)

    The DSI lanes including the CLK lanes MUST be driven to LP11 while the device is in reset until the EN pin

    For your case must be observed requirements from the table below:

    For more information about Hardware Implementation Guide of SN65DSI85 refer to http://www.ti.com/lit/an/slla340a/slla340a.pdf

    Best regards,

    Yanko





  • 0 in reply to Yanko Todorov-XID
    Prodigy 30 points

    Hello Yanko,

    Thanks for your reply.

    Just to give you details, we have DSIA input is connected to OMAP, and only LVDSA has left unconnected. DSIB and LVDSB are both connected.

    Even though DSI1 lines are not used for any data, We are not able to put DSI1 CLK and DSI1 DATA lines to LP11 state due to below reasons.

    1) On Page 2 of SN data sheet, it is shown that SN needs DSI1's CLK to operate in any mode. And PLL_LOCK only happens through DSI1 CLK. So, we can not put DSI1 CLK to LP11 state.

    2) Also, On page 20 of SN65DSI85 below line is written.

    "*VSS and HSS packets are required for DSI Channel B, although LVDS video sync signals are derived from DSI Channel A VSS and HSS packets"

    This means to generate sync signals(while sending data) to LCD on LVDSB, SN needs data(including sync packets) on DSIA. So, if we will put DSI1 data lines to LP11, SN won't generate sync packets to LVDSB.

    Can you please validate if out understanding on above two data points are correct? Also, do you see any operating mode we can use for this configuration?

    Thanks,

    Hardik

  • 0 in reply to Hardik Patel2
    TI__Mastermind 29520 points

    Hi Hardik,

    I had a detail look in SN datasheet and I am agree on your opinion that SN needs DSIA_CLK to operate. If you don't use DSIA channel you must use external reference clock source.

    There are two options for clock configuration of SN.

    1. LVDS clock may be derived from the DSI channel A clock. If the DSI channel A clock is selected, it is divided by the factor in DSI_CLK_DIVIDER (CSR 0x0B.7:3) to generate the FlatLinkTM LVDS output clock.

    2. From external reference clock source - If an external reference clock is selected, it is multiplied by the factor in REFCLK_MULTIPLIER (CSR 0x0B.1:0) to generate the FlatLinkTM LVDS output clock. When an external reference clock is selected, it must be between 25 MHz and 154 MHz.
    Each DSI Channel consists of 4 differential pairs of DSI data lanes and 1 differential pair of DSI CLK lanes. Each LVDS Channel consists of 4 LVDS data lanes and 1 LVDS CLK lane. When 2 DSI Channels are selected for use, the maximum number of data lanes is eight; the maximum number of clock lanes is two, yielding up to 8 Gbps of data throughput.

    About your second assumption concerning VSS and HSS sync signals, I think that, the features for DSI_B channel can set by corresponding CSR registers. Many of the SN65DSI85 functions are controlled by the Control and Status Registers (CSR). All CSR registers are accessible through the local I2C interface.

    I suggest you to take in mind the requirements described in this document - http://www.ti.com/lit/an/slla332b/slla332b.pdf  - SN65DSI8x Video Configuration Guide and Configuration Tool Software Users Manual

    And to download the DSI tuner software from TI website - http://www.ti.com/product/sn65dsi83#technicaldocuments

    LP11 state is from MIPI specification and it is stop state (LP-11). It might be set by I2C command, there is not information about it in SN datasheet and application notes.

    To obtain more information for SN65DSI85, contact with TI sales representative. 

    Best regards,

    Yanko