Basic Question regarding Hyperlink

Hi Sijomon,

Let me address a couple of your questions.

1) The Hyperlink interface has transmit lanes and receive lanes which are connected to second device. Each of the directions has a power management and a flow control sideband bus. These buses are unidirectional and consist of a clock signal and a data signal. These are unique single-ended LVCMOS signals and not a differential pair. The connections of the sideband buses are shown in figure 2-1 of the Hyperlink Users Guide.

3) The reset sequence will prevent any issue with one side being present before the other. Lets assume that we have device A and device B connected with a hyperlink and that device A initiates before device B. Device A will initiate the link by sending a reset command followed by a capabilities/status message. It will then wait for device B to respond with a capabilities/status message. Unfortunately device B isn't ready and nothing happens. Once Device B has been initiated it will send it's own reset command followed by the capabilities/status message. Device A, which has been waiting patiently, receives the reset command and the capabilities/status message, resets the link and responds with a capabilities/status message. Once device B receives this response the link can be completed. This sequence will work regardless of which device initializes first.

4) The statement that you are referring to says the following.

Message 0b1110 is used to transfer four bits of abilities followed by four bits of status. Bit 3 (MSB) of the status message is always zero to prevent the remote device from detecting a reset sequence.

Table 2-2 and 2-3 show the power management and flow control messages. There are fifteen possible messages and a reset command in each table, although many are not used. Seven of these messages and the reset command will have Bit 3 set to a one. The statement above refers only to the status information that follows the 0b1110 Capability/Status Message as shown in the second to last line of tables 2-2 and 2-3. After the 0b1110 message is sent, the four bits of capability and four bits of status information are sent. The ability values are described below Table 2-3.  Since eight bits are being transferred on the sideband, the D3 bit of the four status bits is always zero to prevent the possibility that eight ones would be transferred in response to a capabilities/status message. Eight ones would reset the other end of the link. 

Regards, Bill

Hello Bill,

Thanks for your valuable response. Here are some more questions. Hope you would address these asap.

0) what about points 2 and 4 in previous discussion? Why side band lanes are in pairs? (Page 2-2 of the user manual)

1) what does PLS mean  in page 2-13 of hyperlink user guide

2) in page 2-20 it says, When there is a conflict for the overlay position, it is determined by the following priority order > 1) Security  2) PrivID 3) Address.

Could you explain it a little bit? Because there are many possibilities.

a) The corresponding PrivID bit is ignored / The address bit is ignored

b) The PrivID is shifted left (to the MSB side) / The address bit is shifted further left.

c) The programmer should be cautious and must not put clashing settings. 

d) some thing else!

3) In page 2-24, it says Detection refers to the capturing of either hardware interrupts via the HYPERLINK_INT_I[x] pin or.....

Are these external pins?, How these pins are accessed in the software? Should I read interrupt processing in TMS..6678 to understand what is explained here?

4) EOI function : Doubt at the term "re-enable". Does it mean that,  'if we write to the 'GenSoftIntVal" register with appropriate values(0xFFFF/ 0xFEMN...) and of course with SIEN bit cleared, it will clear the bit in the corresponding INT PENDING/SET register, so that it can be triggered again. For this it is implied that at this time, the bit had already been set in the register by the interrupt input, the interrupt got serviced and the bit in the int pending/set register got cleared, (Who cleared??), but still the input is at high state(level).  If SIEN bit is set, then instead of EOI, it will set the corresponding bit in the INT pending/set register !! .' If this is not the correct interpretation then what is correct?. Anything more which would be useful to me? This document provides lots of room for imagination!! 

5) To where is this Hyperlink_int_o pin routed to? Who will service the Hyperlink_int_o interrupt, to whom this interrupt pin is connected to? Will the corresponding bit in the int pending/set register be cleared automatically after the corresponding interrupt is serviced? 

6) In NySh your code for internal development?. Is there anything as a user we should know about? Nowhere in the document it is mentioned.

7) There are 64 pins/bits in the HW_EVENT reg. and 32 in the int pending/set reg. The mapping won't be exclusive. Also int pending/set register is accessible/settable via remote int packets.So does it mean that the user should use the available resources at his will?

8) How do we configure the Hyperlink_INT[i] pins?

9) Regarding INT STS/CLR register, writing a 1 to the corresponding bit clears the corresponding interrupt. What if I write a 0 to a bit?. When I read a bit from this register what should I infer if I get a 0, and also If the read value is a 1? How does it differ from clearing through INT PRIO STS/CLR register?

10) If I try to send a 32 bit address to the remote device then where is the space for PrivID and Security bit?

11) Can you please explain the sequence of writing an interrupt packet to one of the cores is the remote chip via hyperlink? 

I ask these question because we have a requirement of writing a high level driver to this module. Hope that I would get a prompt response.

thanks and regards,

Sijomon 

now that all setup has been done. How do we initiate a transfer then? Anybody in this world to help???