ARM Cache on OMAPL137

Hi Arthur,

Are you invalidating the instruction cache before enabling the instruction cache. It to make sure that there are no stale contents in the cache. You can look at some sample code provided in SYSBIOS code to see how to safely enable instruction and data cache. Look under the path  packages/ti/sysbios/family/arm/Cache.  I have attached the source file for you reference.

4863.Cache_asm.asm

Hope this helps.

Regards,

Rahul

Hi Rahul,

Thank you for your quick answer.

Effectively I wasn't invalidating the caches before I enable them, but this didn't solve my problem.

I now used the functions from Cache_asm.asm and Mmu_asm.asm to enable both MMU and Caches :

        mov r1, #0
        mcr p15, #0, r1, c8, c7, #0     ; invalidate I+D TLB's

        ldr r0, c_translationTableAddr  ; get page table address
        mcr p15, #0, r0, c2, c0, #0     ; write TTBR with Module->tableBuf.

        sub r1, r1, #1
        mcr p15, #0, r1, c3, c0, #0     ; write domain access regs.

        mrc p15, #0, r0, c1, c0, #0     ; read register c1
        mov r1, #0x1                    ; move #1 into r1
        orr r0, r0, r1                  ; OR r1 with r0 into r0
        mcr p15, #0, r0, c1, c0, #0     ; mmu enabled (bit 1 = 1)

        mrc p15, #0, r1, c1, c0, #0     ; read register c1
        mov r0, #0x0004                 ; set C bit (bit 2) to 1
        orr r1, r1, r0                  ; OR with c1 register
        mcr p15, #0, r1, c1, c0, #0     ; DCache enabled


        mrc p15, #0, r1, c1, c0, #0     ; read register c1
        mov r0, #0x1000                 ; set I bit (bit 12) to 1
        orr r1, r1, r0                  ; OR with c1 register
        mcr p15, #0, r0, c7, c5, #0     ; Invalidate entire instruction cache
        mcr p15, #0, r1, c1, c0, #0     ; ICache enabled

But this doesn't work. In the emulator I cannot access the cached area and when the program jump to a function into this area, I got the following error :

ARM9_0: Trouble Reading Memory Block at 0xc0000000 on Page 0 of Length 0xc: (Error -2030 @ 0x73756C46) Internal error: Access to unknown or invalid register was requested. Restart the application. If error persists, please report the error. (Emulation package 5.0.747.0)

Is there a sample of a complete Translation table with one section set as cacheable and bufferable ?

Or do you have any other Idea of I could have done wrong ?

Best Regards

Arthur

The external SDRAM memory space starts at 0xc0000000, if you access this region without initializing the system PLLs and EMIF interface, you will see that kind of an error. Do you use a GEL file or source code to initialize the external memory interface.

Regards,

Rahul

Hi Rahul,

Yes I use a GEL File to initialize PLLs and the external memory, and the software worked fine (but was too slow) before activation of the MMU and Caches.

Regards

Arthur

Hi Rahul,

I'm thinking that maybe the mistake is in Translation Table I wrote as described in the first message :

"At he address 0x80000000 I have placed the Translation table :

with 4096 entry of the section type.

Possible formats of an entry of the Translation table (I used only Section entry)

• Section base address I started at 0 and then incremented by 1 on each new entry so the Virtual Address equal the Physical Address
• AP : set to 11 so Read and Write are always allowed
• Domain : set to 0 and all domain has been set to read and write allowed
• C and B : set to 00 on each entry except on the line corresponding to the memory where I have placed the code and the data of the function I want to speed up (set to 11 on this line) "

Is there any static example of translation table for OMAPL137 eval Board I could check as example ?

Best regards

Arthur