This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

DDR3 physical length vs electrical length

We are busy designing a PCB with a Sitara AM3x. The design is based on the Beaglebone Black (BBB). Because this is our first design incorporating DDR3, we want to copy the DDR3 placement and routing from the BBB (Altium design files).

When evaluating the design we found the following inconsistency. DDR3 has 3 different clock domains. According to the datasheet of the AM3x the length of the signals in a clock domain should be matched to within 25mils. In the BBB signals from one clock domain run on both top and inner layer. The signals on the top and inner layers are matched to the physical length. To our understanding the propagation times of signals in the top and inner layers differ because of the difference in epsilon r between microstrip and stripline (See http://www.ultracad.com/mentor/microstrip%20propagation.pdf).

The BBB works but shouldn't the traces on top and bottom be matched to electrical length instead of physical length? Or doesn't this matter?

  • Hi Oane,
     
    Several comments from me: The maximum DDR3 clock frequency for the AM335X is 400MHz, rather on the low end of DDR3 frequency range. For DDR3 signal traces impedance requirements are important (typically 50Ohm single-ended, 100Ohm for differential signals, tolerance is +/- 10%), so PCB stack-up should be carefully specified, very likely with the assistance of your PCB vendor. The AM335X Datasheet, Rev.F, Section 5.6.2.3.3 gives all the information necessary for successful DDR3 design. The length matching requirements (Tables 5-66 and 5-67) have been derived based on a large variety of designs and simulations. The purpose is to provide customers with a relatively easy and reliable approach to successful DDR3 design. In your particular case, if you just go ahead and copy the BB Black DDR3 layout, I can assure you that it will work. Trace lengths are very short, so I don't think that differences in propagation times will be of any significance at these frequencies.
  • Hi Biser,

    Thank you for your reply. A PCB vendor made a stackup for us. They specified the trace width and clearance to make 50 ohm and 100 ohm (differential) traces. To make a 100 ohm differential trace we need to put the traces further apart than on the BBB. The result is that we will not meet the trace spacing rules defined in table 5-67. Is this a problem or can we leave it like that?

    We are curious when electrical length becomes important. Could you elaborate a little bit more when electrical length should be taken in to consideration?

  • Hi Oane,
     
    On your first question: There are notes below the tables. What is of interest is Note 10 below Table 5-66 and Note 8 below Table 5-67: "Center-to-center spacing is allowed to fall to minimum (w) for up to 1250 mils of routed length". DDR traces on the BBB are shorter than that, so there should be no issue here.
     
    On the other question: Electrical length for a 400MHz signal is approx. 16200mils. Physical DDR trace lengths on the BBB are in the range of 900mils, which is roughly 5% of the electrical length. Electrical length becomes important at much higher frequencies, when electrical and physical lengths converge. Then it's important to tune the trace so that maximum energy is received at the far end. This is especially true for GHz radio signals in the uV - mV range, where also signal phase has to be taken into account. It's also true for high-speed DDR3 designs with long traces (like computer motherboards).
  • Hi Biser,

    thank you for your time. It's becoming more clear now. It seems I misunderstood note 10, thanks for clarifying.