We are busy designing a PCB with a Sitara AM3x. The design is based on the Beaglebone Black (BBB). Because this is our first design incorporating DDR3, we want to copy the DDR3 placement and routing from the BBB (Altium design files).
When evaluating the design we found the following inconsistency. DDR3 has 3 different clock domains. According to the datasheet of the AM3x the length of the signals in a clock domain should be matched to within 25mils. In the BBB signals from one clock domain run on both top and inner layer. The signals on the top and inner layers are matched to the physical length. To our understanding the propagation times of signals in the top and inner layers differ because of the difference in epsilon r between microstrip and stripline (See http://www.ultracad.com/mentor/microstrip%20propagation.pdf).
The BBB works but shouldn't the traces on top and bottom be matched to electrical length instead of physical length? Or doesn't this matter?