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C5515 DMA interrupt and status bit

Elias Kokkinis
Intellectual 505 points

Hello all,

I am going over the DMA documentation for C5515 once again.

The documentation states that when a block transfer has been completed, the DMA channel issues an interrupt if the corresponding bit is set. This means that when the interrupt is issued, the channel has completed transferring the number of samples specified by the TCR1 register. I have a question: during the interrupt is the corresponding status bit of TCR2 (i.e. bit 14 of DMACHmTCR2) set to 0? This should be so according to SPRUFT2A, 2.10 Monitoring Channel Activity. But inside my interrupt service routing, when I check the STATUS bit it seems it is always 1.

So, what is going on? In other words can the STATUS bit be monitored for polling of DMA transfers?

  • 0
    TI__Genius 12575 points

    Hello Elias,

        If CPU interrupt enable bit ( bit 13 in TCR2) . The DMA channel is capable of generating a CPU interrupt when a block transfer is finished. and regarding the status bit in TCR2.

    The DMA controller clears the STATUS bit to 0 if:

    • All the bytes specified by LENGTH in DMACHmTCR1 have been transferred.

    • A value of 0 is written to LENGTH in DMACHmTCR1.

    If all the bytes are transfer as specified by the length then the status bit will be set to '0', unless auto reload bit is set and the next transfer has began.

    If the above condition is true (auto reload bit set and start of subsequent transfer) then the status reading status bit can reflect '1'.

    Hope the above helps you to resolve the your issue. Please let m e us know if you have further question on this.

    Regards

     Vasanth