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How do I use the full 512 MB space with DDR2?

Other Parts Discussed in Thread: OMAPL138, OMAP-L138

I am designing a board which will require the OMAPL138/C674x processor with 512 MB of DDR2 RAM. It appears that there is no way to use DDR2 chips having 10 bit column addresses since row addresses are limited to 14 bits by the OMAP-L138 pinouts.

Since BA[2] is not used it can be used as a chip select, but this allows only 256 MB addressability. Settings of the SDRC2 register allow for up to 16 bit row addresses, but the address pins allow only 14. If the high order bits appear anywhere I could use them to qualify more chip selects. Do they appear on any pins? 

The problem can be solved if there are DDR2 chips available with 11 bit column address widths - so far I can find only 10 bit widths. Are there any such DDR2 chips with 11 bit column widths (automotive temperature range)?

Of course I could use banking with GPIO pins, though this is not preferable. The manual claims 512MB address space, which I expect would be contiguous.

 

  • Lee,

    Please don’t refer the older version of the datasheet. We are supporting only 256MB of addressable location for the DDR2 memory.

    Please refer the latest version of the datasheet http://www.ti.com/lit/ds/symlink/omap-l138.pdf

    Regards

    Antony

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