TMS320c6678 hyperlink sideband

Hi Bruno,

The timing information in the data manual for the hyperlink sideband signals is correct. This interface does operate at a very high speeds. Traces should be kept a short as possible and the length of the CLK and the DAT lines should be length matched to keep the delay between them at less the 100ps.

Regards, Bill

Hi Bill,

Thank you for your reply.

I still have some worrisome points to ask for:

1) Of course the connections should remain short, but I could read in some document that the recommended length for the MCMLANE diff pairs was about 5cm (max). If we suppose that this corresponds to the distance between transmitter and receiver, the sideband signals would also show the same length. Therefore I consider that 5cm trace length should be adequat for sideband signal.

Don't you agree ?

2) If we consider simulations in order to validate the sideband traces,they are important informations missing in the datasheet :

- What is the voltage threshold applying to timing characterisitic of fig7-42 and 7-43 ?

- What is the load applied to driver output of fig 7-42 ?

- Do you confirm that the sideband protocol is used  in a double data rate fashion , both clock edges being used to transfer data ?

3) In the 6678EVM board we can measure sideband signal length up to 5 cm from DSP to Hyperlink connector.

This results in at least 10cm PCB traces when connecting 2 EVM board together through this hyperlink connector.

Therefore I would expect simulations to be OK up to 10cm trace length in all worst cases.

Do you agree ?

With best regards,

Bruno

Hi Bruno,

First let me give you some additional information on the hyperlink side band signals. The frequency of the sideband signals is based on the Hyperlink data rate that you are using. The timing in the data manual is based on the theoretical maximum wire rate of the serdes interface which is 12.5Gbps. The side band clock rate will be the wire rate divided by 80. For the wire speed of 12.5Gbps, the clock rate is 156.25MHz. For the wire rate of 10Gbps the clock rate is 125MHz.

1)  According to the SerDes Implementation Guide for KeyStone I Devices, the length of the differential pairs should be less than 4” and 2” is recommended. This requirement is strictly for the differential transmit and receive pairs of the serdes lanes and not for the sideband signals. Your 5cm (1.98”) is great for the differential pairs but the side band signals can be longer.

2)  The threshold values for the LVCMOS input are Vih = 0.65 * DVDD18 , Vil = 0.35 * DVDD18. You can use 4pF for the load on the input. The data is driven in a double data rate fashion where both edges are used.

3)  10cm traces for the sideband should be fine. It’s more important that you keep length of the associated clock and data signals matched to within 250ps as specified in the SerDes Implementation Guide. For example, the MCMRXFLCLK & MCMRXFLDAT nets shall be skew matched within 250 ps (absolute maximum) of one another.

Regards, Bill

Hi Bill,

Thank you for the new details you gave.

1) It is a good new that the sideband timing are slightly more relaxed for a link at 10Gb/s than for a link at 12.5 Gb/s.

2) Therefore, at 125MHZ sideband clock, and according to the datasheet, the output driver connected to a 4pF load, will guarantee a level '1' (above 0.65Dvdd18) or level 0 (below 0.35Dvdd18) during 1.6ns before (and after) the clock edge (rising or falling) ...The question being to know where is taken the rising (or falling) edge reference point of the CLK sideband signal. (This reference point is the one used for Tosu and Toh definition)

When examining slow corner case, the rising (or falling) edge are "very long" (about 1ns !) and consequently it  make huge differences depending upon where you take that reference point on the clock egde. This is very critical at the receiver side.

Usually, this reference point is taken where the clock edge crosses the 0.5*Dvdd18 voltage. And looking at the fig.7-42 we can imagine that the vertical dashed line used for Toh and Tosh timing is marvelously placed at that voltage. BUT THIS IS NOT WRITTEN.

==> Do you confirm that the 0.65 and 0.35Dvdd18 thresholds are also used for the clock reference point ? or  is it rather the 0.5*Dvdd18 that is used ?

With best regards,

Bruno

Hi Bruno,

You can assume that the timing point for the threshold is DVDD18/2. The IO cell does have hysteresis so there is a 200mV difference between the rising edge threshold and the falling edge threshold but for timing it's best to use the DVDD18/2 as a reference. The data signal is delayed from the clock signal at the driver. With properly length matched traces this will guarantee that the setup and hold times should be met at the receiver.

Regards, Bill 

Hi Bill,

Everything has been clarified now concerning the sideband signals.

About Hyperlink itself, don't you have any new information about the receiver compliancy mask (see my previous post : TMS320C6678 Hyperlink receiver). I am still looking for this characteristic.

Best regards,

Bruno