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OMAPL138 AINTC CMR

Hongbo Dai1
Prodigy 60 points

 

 

 

Hi,

   I can not understand the CMR register.  and the N represents what ?     CHNL_NPLUS  set for the host interrupt?   what is the relatioship between the CMR[n] and  The 101 system interrupt ?  I am confused. who can help  me ?

  • 0
    TI__Mastermind 43955 points

    Hi Hongbo Dai,

    I went through the TRM, at a first sight, I thought it could be an error in the documentaion. i.e., as N represents the 101 system interrupts, the CHNL_NPLUS1,2,3 should have the descriptions like "sets the channel for the system interrupt N+1, N+2 and N+3" respectively.

    But, I could not find any separate Host interrupt mapped registers for mapping the Host interrupts; this leads to me to think, whether in AINTC, the channel mapped registers are commonly used for both system and Host interrupts?...( which most probably cannot be the case)

    Please hold on for a while until I confirm it as a documentation error. Let me check with the team and get back to you.

    A sample timer application is available in the starterware to demonstrate the interrupt processing. please have a look at the source code of it to know how the channel numbers are set and the registers are configured for system interrupts. http://processors.wiki.ti.com/index.php/StarterWare_01.10.01.01_User_Guide#Example_Configuration

     

    Regards,

    Shankari.