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SYS/BIOS MMC on AM3359

Other Parts Discussed in Thread: AM3359, SYSBIOS

We are converting our StarterWare program(AM335X_StarterWare_02_00_00_07\build\armv7a\cgt_ccs\am335x\evmAM335x\hs_mmcsd) to run on SYS/BIOS 6.35.3.47.The issue we are running into is that MMC write or read. When executing the following code before read MMC,and i can read the correct data from the MMC.

attrs.type = Mmu_FirstLevelDesc_SECTION; 

attrs.domain = 0;

attrs.imp = 1;

attrs.accPerm = 3;   

 for (i=0x80000000;i<0x90000000;i=i+0x00100000) {  

// Each 'SECTION' descriptor entry spans a 1MB address range        

attrs.bufferable =0;        

attrs.cacheable =0;        

Mmu_setFirstLevelDesc((Ptr)(i), (Ptr)(i) , &attrs); }

However, in this state Cache is disable,and AM3359 low operating efficiency.

When executing the following code before read MMC,and i can't read the correct data from the MMC.

attrs.type = Mmu_FirstLevelDesc_SECTION; 

attrs.domain = 0;

attrs.imp = 1;

attrs.accPerm = 3;    

for (i=0x80000000;i<0x90000000;i=i+0x00100000) {  

// Each 'SECTION' descriptor entry spans a 1MB address range        

attrs.bufferable =1;        

attrs.cacheable =1;        

 Mmu_setFirstLevelDesc((Ptr)(i), (Ptr)(i) , &attrs); }

I need help!

This is my first message here, my English is poor, please forgive me.  

Thanks!

LiZhan.

 

  • Hi LiZhan,

    Cdoc (ti.sysbios.family.arm.a8.Mmu) says :

    If the 'cacheable' attribute is true and 'bufferable' is true, L1 data cache operates as a write-back cache. If 'cacheable' is true but 'bufferable' is false, L1 data cache operates as a write-through cache.

    So you are configuring cache as write-back mode for external memory.
    In this case, you would need to manage the cache coherency by yourself.
    If you use write-through cache, I think the write operation can be reached to both cache and physical memory.
    Please try to use write-through cache at once and see if it works or not.

    Hope this helps.

    Regards,

    Kawada 

  • Hi Kawada,

    I tested. When configured Cache as  write-through mode,it worked.However, in this mode, the speed is too slow.

    I have to use write-back mode,How do I manage Cache.where can I find out relevant examples?

     

     

    Thanks!

    LiZhan.

  • HI LiZhan,

    The smaller performance is expected when using write-through cache.
    Now you found the root cause was the cache coherency issue.
    You can handle cache coherency with Cache_wb, Cache_wbInv and Cache_inv etc...
    Please go to Cdoc (ti.sysbios.hal.Cache) and check the usage of these functions.

    Regards,
    Kawada 

  • Hi Kawada,

    I have solved the problem.

    Thanks very much.

    LiZhan