Hi, all
Environment description: Boot from SPI flash directly(no ibl, not evm). C6670 DSP.
We have finished booting the 4 cores, using a HelloWorld simple project. And we solved the address problem through changing the package and cmd file of the project.
When we boot our own project, we can go into main() funtion. But when the code allocate the DDR memory, a hint was shown: "[C66xx_0] ti.sysbios.heaps.HeapMem: line 307: out of memory: handle=0x10869318, size=1030464
xdc.runtime.Error.raise: terminating execution" We guess there is something wrong with the heap. The shown length is a bit larger than our definition. Something odd is that when we use the emulator to connect the DSP, it runs successfully and there is no error occured. Our gel file is similar to the 6670EVM gel file with some ddr configuration changes. We guess that there is something of the DDR config we have never noticed.
Here is part of "tiboot.h" file from the attached example "7080.SPIboot_ddr.zip"
/*******************************************************************************
* Emif4 (DDR3) configuration table
*******************************************************************************/
typedef struct bootEmif4Tbl_s {
UINT32 configSelect_msw; /* Bit map defining which registers to set */
UINT32 configSelect_slsw; /* Bit map defining which registers to set */
UINT32 configSelect_lsw; /* Bit map defining which registers to set */
UINT32 pllPrediv; /* Values of all 0s will disable the pll */
UINT32 pllMult;
UINT32 pllPostDiv;
UINT32 sdRamConfig; /* Controlled by bit 1 of configSelect_msw */
UINT32 sdRamConfig2; /* Bit 2 */
UINT32 sdRamRefreshCtl; /* Bit 3 */
UINT32 sdRamTiming1; /* Bit 4 */
UINT32 sdRamTiming2; /* Bit 5 */
UINT32 sdRamTiming3; /* Bit 6 */
UINT32 lpDdrNvmTiming; /* Bit 7 */
UINT32 powerManageCtl; /* Bit 8 */
UINT32 iODFTTestLogic; /* Bit 9 */
UINT32 performCountCfg; /* Bit 10 */
UINT32 performCountMstRegSel; /* Bit 11 */
UINT32 readIdleCtl; /* Bit 12 */
UINT32 sysVbusmIntEnSet; /* Bit 13 */
UINT32 sdRamOutImpdedCalCfg; /* Bit 14 */
UINT32 tempAlterCfg; /* Bit 15 */
UINT32 ddrPhyCtl1; /* Bit 16 */
UINT32 ddrPhyCtl2; /* Bit 17 */
UINT32 priClassSvceMap; /* Bit 18 */
UINT32 mstId2ClsSvce1Map; /* Bit 19 */
UINT32 mstId2ClsSvce2Map; /* Bit 20 */
UINT32 eccCtl; /* Bit 21 */
UINT32 eccRange1; /* Bit 22 */
UINT32 eccRange2; /* Bit 23 */
UINT32 rdWrtExcThresh; /* Bit 24 */
UINT32 chipConfig[64];
} BOOT_EMIF4_TBL_T;
Here is part of "toboot.h" file from 6670 bootloader source code("C6670_pg10_bootloader.zip")
/*******************************************************************************
* Emif4 (DDR3) configuration table
*******************************************************************************/
typedef struct bootEmif4Tbl_s {
UINT32 configSelect; /* Bit map defining which registers to set */
UINT32 pllPrediv; /* Values of all 0s will disable the pll */
UINT32 pllMult;
UINT32 pllPostDiv;
UINT32 sdRamConfig;
UINT32 sdRamConfig2;
UINT32 sdRamRefreshCtl;
UINT32 sdRamTiming1;
UINT32 sdRamTiming2;
UINT32 sdRamTiming3;
UINT32 lpDdrNvmTiming;
UINT32 powerManageCtl;
UINT32 iODFTTestLogic;
UINT32 performCountCfg;
UINT32 performCountMstRegSel;
UINT32 readIdleCtl;
UINT32 sysVbusmIntEnSet;
UINT32 sdRamOutImpdedCalCfg;
UINT32 tempAlterCfg;
UINT32 ddrPhyCtl1;
UINT32 ddrPhyCtl2;
UINT32 priClassSvceMap;
UINT32 mstId2ClsSvce1Map;
UINT32 mstId2ClsSvce2Map;
UINT32 eccCtl;
UINT32 eccRange1;
UINT32 eccRange2;
UINT32 rdWrtExcThresh;
} BOOT_EMIF4_TBL_T;
We can see there are something different between the two parts. We are using the 6670 bootloader version and it worked till now(DDR can be read and written correctly). Our question is: Should we config the UINT32 chipConfig[64] . part of DDR? If so, how to config? If not, how can we solved this heap problem? We guess there is something wrong with this part because the gel file has do some part of config in UINT32 chipConfig[64] .
Another question: We know that before loading codes to L2 and DDR, we should config the PLL(using boot parameter table) and DDR(in this case, using emif4 config table). Is there anyting we should config before bootloading except for PLL and DDR? If so, how to do the conifg?
Waiting for your reply, it's urgent. Thank you for you patience.
Karlphy