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Keystone II Memory coherency

Other Parts Discussed in Thread: TCI6638K2K

In TCI6638K2K Data Manual, the Memory Map section said that the memory region  60000000 to 7FFFFFFF is No IO coherency supported for this region. What does this really mean? Does this mean even the memory attribute set to shared, it also need cache maintenance operation for it?

  • Hi Zhigang,

    The section 2.4 MSMC IO Coherence of the SPRUHJ6 (KeyStone II Architecture Multicore Shared Memory Controller (MSMC) User Guide) explains the topic much clearly.

    Accessing DDR3A or DDR3B via the address range 0x00_6000_0000 to 0x00_7fff_ffff, memory coherency between the ARM CorePac L1/L2 caches and the memory is NOT maintained by hardware.

    On the other hand, DDR3A access through the address range 0x08_0000_0000 to the 0x09_ffff_ffff can be maintained coherent, to my understanding.  (Please refer the above manual.)

    Regards,
    Atsushi