DM3730 to configure McBSP3

I think I may make some grammer mistake in the code above. So I change them as below:

struct omap_mcbsp_reg_cfg mcbsp_cfg = {

.spcr1 = RJUST(0) | DXENA | RINTM(2),

.spcr2 = FREE | SOFT | XINTM(2) | XSYNC_ERR,

.pcr0 = FSXM | FSRM | CLKXM | CLKRM | CLKRP,

.rcr1 = RFRLEN1(7) | RWDLEN1(0),

.rcr2 = RPHASE | RFRLEN2(7) | RWDLEN2(0) | RCOMPAND(0) | RDATDLY(1),

.xcr1 = XFRLEN1(7) | XWDLEN1(0),

.xcr2 = XPHASE | XFRLEN2(7) | XWDLEN2(0) | XCOMPAND(0) | XDATDLY(1),

.srgr1 = FWID(7) | CLKGDV(186),

.srgr2 = FSGM | FPER(7),

};

But I can't get the output from FSX still. Pls help me! Thank you!

BR

John

Hi John,

I found a configuration of the McBSP registers which has been used in a test application. There are the values of the most notable registers used in the test application:

SPCR1 = 0x01
SPCR2 = 0x01C3
RCR1  = 0x40
RCR2  = 0x01
XCR1  = 0x40
XCR2  = 0x01
SRGR1 = 0x108   If you set CLKGDV with 186 the recommended value for SRGR1 is 0x1BA
SRGR2 = 0x3011

Could you dump the register values in your application to compare with these values?

I only would like to add that an other possible reason for the absence of output signal could be in the schematics and connections.

BR

Tsvetolin Shulev

Be glad to see your reply.

My configuration is to set the register of McBSP3 as below:

struct omap_mcbsp_reg_cfg mcbsp_cfg = { 
.spcr1 = RJUST(0) | DXENA | RINTM(2),
.spcr2 = FREE | SOFT | XINTM(2) | XSYNC_ERR,
.pcr0 = FSXM | FSRM | CLKXM | CLKRM | CLKRP,
.rcr1 = RFRLEN1(0) | RWDLEN1(0),
.rcr2 = RPHASE | RFRLEN2(0) | RWDLEN2(0) | RCOMPAND(0) | RDATDLY(0),
.xcr1 = XFRLEN1(0) | XWDLEN1(0),
.xcr2 = XPHASE | XFRLEN2(0) | XWDLEN2(0) | XCOMPAND(0) | XDATDLY(0),
.srgr1 = FWID(7) | CLKGDV(186),
.srgr2 = FSGM | FPER(7),
};

Then I use the following code to initialize McBSP3:

mcbsp_id = OMAP_MCBSP3;
status = omap_mcbsp_request(mcbsp_id);
printk(KERN_ALERT "First cfg:\n");
DumpMcBSP_cfg();  //Dump all register value
omap_mcbsp_config(mcbsp_id, &mcbsp_cfg);
mdelay(1); //Wait for more than 2 clocks
mcbsp_cfg.srgr2 |= GSYNC;
printk(KERN_ALERT "Second cfg:\n");
DumpMcBSP_cfg();
omap_mcbsp_config(mcbsp_id, &mcbsp_cfg);
mdelay(1);

mcbsp_cfg.spcr1 |= RRST;

mcbsp_cfg.spcr2 |= XRST;
printk(KERN_ALERT "Third cfg:\n");
DumpMcBSP_cfg();
omap_mcbsp_config(mcbsp_id, &mcbsp_cfg);
mcbsp_cfg.spcr2 |= FRST;
mcbsp_cfg.spcr2 |= GRST; 
printk(KERN_ALERT "Fourth cfg:\n");
DumpMcBSP_cfg();
omap_mcbsp_config(mcbsp_id, &mcbsp_cfg);
mdelay(1); 
omap_mcbsp_set_io_type(mcbsp_id, OMAP_MCBSP_POLL_IO);

The output of the code above are:

First cfg:
spcr1=a0
spcr2=328
pcr0=f01
rcr1=0
rcr2=8000
xcr1=0
xcr2=8000
srgr1=7ba
srgr2=1007
Second cfg:
spcr1=a0
spcr2=328
pcr0=f01
rcr1=0
rcr2=8000
xcr1=0
xcr2=8000
srgr1=7ba
srgr2=9007
Third cfg:
spcr1=a1
spcr2=329
pcr0=f01
rcr1=0
rcr2=8000
xcr1=0
xcr2=8000
srgr1=7ba
srgr2=9007
Fourth cfg:
spcr1=a1
spcr2=3e9
pcr0=f01
rcr1=0
rcr2=8000
xcr1=0
xcr2=8000
srgr1=7ba
srgr2=9007

You can see no value same as you provided. I try to set the register as the value in your last reply. Then the system halt when execute the first omap_mcbsp_config(). Why?

I hope I can see your reply as soon. Thank you!

BR!

John

Hello Cvetolin,

My problem is still exist. More help will be appreciated.

I had tried to fix it by changing the configuration of multiplex. I noticed McBSP3_fsx share the same pin with HsUSB3_tll_data7. Then I find and change the configuration of hsusb3. But nothing happened. Maybe this signal is conflicted with Uart2, isn't it?

The most important thing is, McBSP3_clkx can work correctly now. In the datasheet of DM3730, I notice that McBSP3_fsx and McBSP3_clkx are stem from the same internal signal SRG. In advanced, I can set the polarity of fsx by set or clear PCR.FSXP. I think this means the multiplex of McBSP3 is correct. The configuration of the gate along the path of fsx is correct too. I'm confused that what make McBSP3.fsx can't work? I need more help! Thx!

BR

John

Hi John,

You should check pinmux configuration in both u-boot and kernel because you could have correct McBSP3 pinmux in the u-boot but then it could be changed in the kernel. If you think that all with the pinmux is correct you can configure digital loop back mode to test whether your configuration is right (if you receive sent data). More details about digital loop back mode you can find in the TRM section 21.5.1.5.2.1.2 Enable/Disable the Digital Loop Back Mode.

This test targets to localize where is the problem - is it configuration issue or is it out of the processor.

BR

Tsvetolin Shulev

Hi Mr. Shulev,

I'm still research this problem. I had try to set XCCR.DLB as your advise. But the board can't boot then.

I had read the DS of dm3730. In section 21.4.3.2, it say I must clear SPCR2.FRST to enable SRG, although in the description of SPCR2, it says that SPCR2.FRST=0 will prevent the generation of FSG. I am confused about this conflicting. Now I configuration the McBSP3 as 21.4.3.2, but nothing get right.

In section 21.4.3.3, it's said that SPGR2.GSYNC should be clear to make CLKG runs freely and SPGR2.FPER can't be ignored. This means if I do as it, the signal FSX will work as I expected, isn't it? Could u be kind to teach me? Thank you!

BR

John