Hi,
Looking at the May 2013 Errata for the C6678 (is there a way to get an e-mail when TI updates a document? It would seem an obvious thing to have but I can't find a way to subscribe to a document...), I see that, under Advisory 27, it says:
Note on coherence operations:
For the following advisory , double MFENCE can also be used as a workaround in addition to the workarounds already listed:
• Advisory 7—Potential L2 Cache Corruption During Block Coherence Operations Issue
• Advisory 22—L2 Cache Corruption During Block and Global Coherence Operations Issue
Does this mean that, in the following workaround from Advisory 22 for example, the 16 NOPs in step 5 can be replaced by a second MFENCE?
1. Disable interrupts.
2. Write the starting address to the corresponding BAR register.
3. Write the word count to the corresponding WC register
4. Wait for completion by one of the following methods
a. Issue an MFENCE instruction (preferred)
b. Poll the WC register until the word count field reads as 0
5. Perform 16 NOPs
6. Restore interrupts
Thanks,
SPH
