Hi,
my configuration is a C6457 that boots a C6474 using RapidIO Boot Configuration 0 (1.25Gpbs). The 2 devices are on the same board.
The data throughput with NWRITE is about 600MBit/s; I get a shorter boot time (and about 950MBit/s) between two other C6457+C6474 on the same board. the schematics of the 2 couples are almost identical, but the placement is different.
I'm trying to figure out why.
On the C6457 we get an ERR_IMP_SPECIFIC=1 and SP0_ERR_STAT bit 26 =1. This indicates an UDI Ingress timeout (see http://e2e.ti.com/support/dsp/c6000_multi-core_dsps/f/439/p/48493/171888.aspx).
But why can I have a congestion at the input of C6457, when C6474 is a slave device executing the ROM bootloader code?
Can signal integrity problem on the line cause this effect? Shouldn't I be able to detect CRC errors in SP0_ERR_DET?
In most cases, the only active flag in SP0_ERR_DET is bit 31 (ERR_IMP_SPECIFIC); sometimes also bit 20 RCVED_PKT_NOT_ACCPT. Enabling the error counters in SP0_ERR_RATE, I easily reach the threshold for ERR_IMP_SPECIFIC, but I get only a few RCVED_PKT_NOT_ACCPT.
Thanks
Massimo