See http://e2e.ti.com/support/embedded/starterware/f/790/p/289661/1012979.aspx for background; I am maintaining the thread in this forum because the problem might be hardware-related.
I'm pretty sure my new board (a custom board, not the EVM) has a
memory access problem somehow.
I tried Getting_Started.ewp at
C:\Program Files (x86)\IAR Systems\Embedded Workbench 6.5\arm\examples\TexasInstruments\AM335x\AM335x_EVM\Getting_Started\
and deselected "Run to main" in Project-Options - Debugger. I am
now running IAR ver 6.50.6.4958; the problem is the same as in
ver 6.60.
In the below, it hangs on the line:
0x402f04d0: 0x1bfffff9 BLNE ?Veneer (1) for __iar_data_init3 ; 0x402f04bc
At ?Veneer (1) for __iar_data_init3 is the first access to
memory rather than a register. I'm not sure why it's hanging on
the branch rather than on the "LDR PC, [PC, #-0x4]"
instruction, however.
Please see my previous messages above in this thread for what I
have set.
Selecting the "Code Coverage" plugin doesn't seem to make any
difference. I'm not using the macro file: Disable_WDT.mac.
The voltages are, on my new board:
VDDSHV1/GPMC = VDIG1= 2.24V
VDDSHV2/MMCSD-B = VMMC = 3.3V
VDDSHV3/GEMAC-B = VMMC = 3.3V
VDDSHV4/MMCSD-A = VMMC = 3.3V
VDDSHV5/GEMAC-A = VMMC = 3.3V
VDDSHV6/GENERAL = VAUX2 = 3.3V
VDDSHV1 should be 3.3V; would this cause a problem? I am getting
that fixed. Can any software problem be causing this?
I seem to be able to write bytes to the stack area of memory
using the debugger.
We are going to be a paying customer of TI, buying AM3359 micros
for these boards when we get them working, so we need this issue
solved.
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?cstartup:
__iar_program_start:
0x402f043c: 0xe10f0000 MRS R0, CPSR
BIC r0, r0, #MODE_MSK ; Clear the mode bits
0x402f0440: 0xe3c0001f BIC R0, R0, #31 ; 0x1f
ORR r0, r0, #IRQ_MODE ; Set IRQ mode bits
0x402f0444: 0xe3800012 ORR R0, R0, #18 ; 0x12
MSR cpsr_c, r0 ; Change the mode
0x402f0448: 0xe121f000 MSR CPSR_c, R0
LDR sp, =SFE(IRQ_STACK) ; End of IRQ_STACK
0x402f044c: 0xe59fd034 LDR SP, _?0 ; FIQ_STACK$$Base
BIC sp,sp,#0x7 ; Make sure SP is 8 aligned
0x402f0450: 0xe3cdd007 BIC SP, SP, #7
BIC r0, r0, #MODE_MSK ; Clear the mode bits
0x402f0454: 0xe3c0001f BIC R0, R0, #31 ; 0x1f
ORR r0, r0, #FIQ_MODE ; Set FIR mode bits
0x402f0458: 0xe3800011 ORR R0, R0, #17 ; 0x11
MSR cpsr_c, r0 ; Change the mode
0x402f045c: 0xe121f000 MSR CPSR_c, R0
LDR sp, =SFE(FIQ_STACK) ; End of FIQ_STACK
0x402f0460: 0xe59fd024 LDR SP, _?1 ; FIQ_STACK$$Limit
BIC sp,sp,#0x7 ; Make sure SP is 8 aligned
0x402f0464: 0xe3cdd007 BIC SP, SP, #7
BIC r0 ,r0, #MODE_MSK ; Clear the mode bits
0x402f0468: 0xe3c0001f BIC R0, R0, #31 ; 0x1f
ORR r0 ,r0, #SYS_MODE ; Set System mode bits
0x402f046c: 0xe380001f ORR R0, R0, #31 ; 0x1f
MSR cpsr_c, r0 ; Change the mode
0x402f0470: 0xe121f000 MSR CPSR_c, R0
LDR sp, =SFE(CSTACK) ; End of CSTACK
0x402f0474: 0xe59fd014 LDR SP, _?2 ; CSTACK$$Limit
BIC sp,sp,#0x7 ; Make sure SP is 8 aligned
0x402f0478: 0xe3cdd007 BIC SP, SP, #7
BL __iar_init_core
0x402f047c: 0xe1a00000 MOV R0, R0
BL __iar_init_vfp
0x402f0480: 0xeb000003 BL __iar_init_vfp_v6 ; 0x402f0494
B __cmain
0x402f0484: 0xea00000e B ?main ; 0x402f04c4
_?0:
0x402f0488: 0x40309308 DC32 FIQ_STACK$$Base
_?1:
0x402f048c: 0x40309348 DC32 FIQ_STACK$$Limit
_?2:
0x402f0490: 0x40309208 DC32 CSTACK$$Limit
__iar_init_vfp_v6:
0x402f0494: 0xee110f50 MRC p15, #0, R0, C1, C0, #2
0x402f0498: 0xe38008f0 ORR R0, R0, #15728640 ; 0xf00000
0x402f049c: 0xee010f50 MCR p15, #0, R0, C1, C0, #2
0x402f04a0: 0xe3a00001 MOV R0, #1
0x402f04a4: 0xee070f95 MCR p15, #0, R0, C7, C5, #4
__iar_init_vfp:
0x402f04a8: 0xe3a00440 MOV R0, #1073741824 ; 0x40000000
0x402f04ac: 0xeee80a10 VMSR FPEXC, R0
0x402f04b0: 0xe3a007c0 MOV R0, #50331648 ; 0x3000000
0x402f04b4: 0xeee10a10 VMSR FPSCR, R0
0x402f04b8: 0xe12fff1e BX LR
?Veneer (1) for __iar_data_init3:
0x402f04bc: 0xe51ff004 LDR PC, [PC, #-0x4] ; [0x402f04c0] __iar_data_init3
0x402f04c0: 0x402f04ed DC32 __iar_data_init3
?main:
__cmain:
0x402f04c4: 0xe3a00001 MOV R0, #1
0x402f04c8: 0xfa000006 BLX __low_level_init ; 0x402f04e8
0x402f04cc: 0xe3500000 CMP R0, #0
0x402f04d0: 0x1bfffff9 BLNE ?Veneer (1) for __iar_data_init3 ; 0x402f04bc
_call_main:
0x402f04d4: 0xe3a00000 MOV R0, #0
0x402f04d8: 0xfb000162 BLX main ; 0x402f0a6a
_main:
0x402f04dc: 0xfa0001dd BLX exit ; 0x402f0c58
0x402f04e0: 0xeb0001de BL __exit ; 0x402f0c60
0x402f04e4: 0xeafffffd B 0x402f04e0
__low_level_init:
0x402f04e8: 0x2001 MOVS R0, #1
0x402f04ea: 0x4770 BX LR
__iar_data_init3:
0x402f04ec: 0xb510 PUSH {R4, LR}
0x402f04ee: 0x4907 LDR.N R1, [PC, #0x1c] ; [0x402f050c] 0xd44 (3396)
0x402f04f0: 0x4479 ADD R1, R1, PC
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