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AM335x can't call a function

Other Parts Discussed in Thread: AM3359, AM3358

See http://e2e.ti.com/support/embedded/starterware/f/790/p/289661/1012979.aspx for background; I am maintaining the thread in this forum because the problem might be hardware-related.

I'm pretty sure my new board (a custom board, not the EVM) has a
memory access problem somehow.
I tried Getting_Started.ewp at
C:\Program Files (x86)\IAR Systems\Embedded Workbench 6.5\arm\examples\TexasInstruments\AM335x\AM335x_EVM\Getting_Started\
and deselected "Run to main" in Project-Options - Debugger. I am
now running IAR ver 6.50.6.4958; the problem is the same as in
ver 6.60.
In the below, it hangs on the line:
0x402f04d0: 0x1bfffff9 BLNE ?Veneer (1) for __iar_data_init3 ; 0x402f04bc
At ?Veneer (1) for __iar_data_init3 is the first access to
memory rather than a register. I'm not sure why it's hanging on
the branch rather than on the "LDR PC, [PC, #-0x4]"
instruction, however.
Please see my previous messages above in this thread for what I
have set.
Selecting the "Code Coverage" plugin doesn't seem to make any
difference. I'm not using the macro file: Disable_WDT.mac.

The voltages are, on my new board:

VDDSHV1/GPMC = VDIG1= 2.24V

VDDSHV2/MMCSD-B = VMMC = 3.3V

VDDSHV3/GEMAC-B = VMMC = 3.3V

VDDSHV4/MMCSD-A = VMMC = 3.3V

VDDSHV5/GEMAC-A = VMMC = 3.3V

VDDSHV6/GENERAL = VAUX2 = 3.3V

VDDSHV1 should be 3.3V; would this cause a problem? I am getting
that fixed. Can any software problem be causing this?
I seem to be able to write bytes to the stack area of memory
using the debugger.
We are going to be a paying customer of TI, buying AM3359 micros
for these boards when we get them working, so we need this issue
solved.

-----------------------------------------------------------------
?cstartup:
__iar_program_start:
0x402f043c: 0xe10f0000 MRS R0, CPSR
BIC r0, r0, #MODE_MSK ; Clear the mode bits
0x402f0440: 0xe3c0001f BIC R0, R0, #31 ; 0x1f
ORR r0, r0, #IRQ_MODE ; Set IRQ mode bits
0x402f0444: 0xe3800012 ORR R0, R0, #18 ; 0x12
MSR cpsr_c, r0 ; Change the mode
0x402f0448: 0xe121f000 MSR CPSR_c, R0
LDR sp, =SFE(IRQ_STACK) ; End of IRQ_STACK
0x402f044c: 0xe59fd034 LDR SP, _?0 ; FIQ_STACK$$Base
BIC sp,sp,#0x7 ; Make sure SP is 8 aligned
0x402f0450: 0xe3cdd007 BIC SP, SP, #7
BIC r0, r0, #MODE_MSK ; Clear the mode bits
0x402f0454: 0xe3c0001f BIC R0, R0, #31 ; 0x1f
ORR r0, r0, #FIQ_MODE ; Set FIR mode bits
0x402f0458: 0xe3800011 ORR R0, R0, #17 ; 0x11
MSR cpsr_c, r0 ; Change the mode
0x402f045c: 0xe121f000 MSR CPSR_c, R0
LDR sp, =SFE(FIQ_STACK) ; End of FIQ_STACK
0x402f0460: 0xe59fd024 LDR SP, _?1 ; FIQ_STACK$$Limit
BIC sp,sp,#0x7 ; Make sure SP is 8 aligned
0x402f0464: 0xe3cdd007 BIC SP, SP, #7
BIC r0 ,r0, #MODE_MSK ; Clear the mode bits
0x402f0468: 0xe3c0001f BIC R0, R0, #31 ; 0x1f
ORR r0 ,r0, #SYS_MODE ; Set System mode bits
0x402f046c: 0xe380001f ORR R0, R0, #31 ; 0x1f
MSR cpsr_c, r0 ; Change the mode
0x402f0470: 0xe121f000 MSR CPSR_c, R0
LDR sp, =SFE(CSTACK) ; End of CSTACK
0x402f0474: 0xe59fd014 LDR SP, _?2 ; CSTACK$$Limit
BIC sp,sp,#0x7 ; Make sure SP is 8 aligned
0x402f0478: 0xe3cdd007 BIC SP, SP, #7
BL __iar_init_core
0x402f047c: 0xe1a00000 MOV R0, R0
BL __iar_init_vfp
0x402f0480: 0xeb000003 BL __iar_init_vfp_v6 ; 0x402f0494
B __cmain
0x402f0484: 0xea00000e B ?main ; 0x402f04c4
_?0:
0x402f0488: 0x40309308 DC32 FIQ_STACK$$Base
_?1:
0x402f048c: 0x40309348 DC32 FIQ_STACK$$Limit
_?2:
0x402f0490: 0x40309208 DC32 CSTACK$$Limit
__iar_init_vfp_v6:
0x402f0494: 0xee110f50 MRC p15, #0, R0, C1, C0, #2
0x402f0498: 0xe38008f0 ORR R0, R0, #15728640 ; 0xf00000
0x402f049c: 0xee010f50 MCR p15, #0, R0, C1, C0, #2
0x402f04a0: 0xe3a00001 MOV R0, #1
0x402f04a4: 0xee070f95 MCR p15, #0, R0, C7, C5, #4
__iar_init_vfp:
0x402f04a8: 0xe3a00440 MOV R0, #1073741824 ; 0x40000000
0x402f04ac: 0xeee80a10 VMSR FPEXC, R0
0x402f04b0: 0xe3a007c0 MOV R0, #50331648 ; 0x3000000
0x402f04b4: 0xeee10a10 VMSR FPSCR, R0
0x402f04b8: 0xe12fff1e BX LR
?Veneer (1) for __iar_data_init3:
0x402f04bc: 0xe51ff004 LDR PC, [PC, #-0x4] ; [0x402f04c0] __iar_data_init3
0x402f04c0: 0x402f04ed DC32 __iar_data_init3
?main:
__cmain:
0x402f04c4: 0xe3a00001 MOV R0, #1
0x402f04c8: 0xfa000006 BLX __low_level_init ; 0x402f04e8
0x402f04cc: 0xe3500000 CMP R0, #0
0x402f04d0: 0x1bfffff9 BLNE ?Veneer (1) for __iar_data_init3 ; 0x402f04bc
_call_main:
0x402f04d4: 0xe3a00000 MOV R0, #0
0x402f04d8: 0xfb000162 BLX main ; 0x402f0a6a
_main:
0x402f04dc: 0xfa0001dd BLX exit ; 0x402f0c58
0x402f04e0: 0xeb0001de BL __exit ; 0x402f0c60
0x402f04e4: 0xeafffffd B 0x402f04e0
__low_level_init:
0x402f04e8: 0x2001 MOVS R0, #1
0x402f04ea: 0x4770 BX LR
__iar_data_init3:
0x402f04ec: 0xb510 PUSH {R4, LR}
0x402f04ee: 0x4907 LDR.N R1, [PC, #0x1c] ; [0x402f050c] 0xd44 (3396)
0x402f04f0: 0x4479 ADD R1, R1, PC
-----------------------------------------------------------------

  • Definitely VDDSHV1 should not be 2.24V. The allowed voltages are either 1.8V or 3.3V. For external memory there is a wiki page describing how to tune it, and also a step-by-step tutorial for DDR3 tuning:
  • Everything for now is in internal memory, from 0x402F0400 to 0x4030FFFF. What kind of info about internal memory can you point me to?
    The IAR debugger is putting ROM in 0x402F0400 to 0x40307FFF and RAM in 0x40308000 to 0x4030FFFF. All this is RAM in the AM335x. Would the bad voltage cause problems with internal memory? I seem to be able to write to this area using the debugger; why do you suppose an instruction would have trouble?

    Best regards,

  • As best as I can determine from my hardware guy, and checking the voltages myself, the voltages have been fixed on repaired boards that I received yesterday, but this problem persists. I wonder if bizarre instruction problems like these can be caused by the experimental AM335x micro that I have? I also cannot get through a PUSH {R7, LR} instruction in other code, that gets put in before function calls. I have the XAM3359ZCZ (model code copied right off of the chip) micro on my boards, which has silicon rev 1.0.

    Best regards,

  • Any ideas?

  • I am not running Linux and am not trying to access SDRAM, I don't think... I
    have custom hardware that is modeled after the TI TMDXEVM3358-SK-LCD evaluation
    module. I have just started on it and can connect with the debugger; I am using
    IAR, with very small test programs. Code that runs in main() can access hardware
    registers and get through while loops, but when I put that code into a function,
    execution hangs on a PUSH instruction that the compiler puts there before
    branching to the function. That still happens even when I make the function
    trivial, empty.
    All this code can run in the EVM.
    Trying some Starterware code, I get a hang on a BLNE instruction before it even
    gets to "main:". A semi-trivial program that just runs in a loop and increments
    two variables and tests them hung on a CMP R0,R2 instruction every time I tried
    it, for a few days. Later the loop worked. Also later the partial Startware code
    hung on a different branch instruction before getting to "main:".
    I have not yet managed to enable the regulator that supplies the voltage to the
    DDR3 SDRAM, and as far as I know, my simple programs are running in the micro's
    SRAM starting at 0x402F0400.
    It sure looks like a problem with the micro, and we are having our boards
    reworked to get a non-experimental micro, preferably silicon rev 2.1, but I want
    to make sure that I am doing all that I can to get code running, myself.

  • If the example code runs on an EVM but not on your hardware this suggests one of two things to me:

    1. The code has some hardware dependencies for the EVM which your board does not replicate (as an example, I2C configuration calls to a PMIC).
    2. Issues with the hardware itself.

    It seems like you have already found at least one hardware problem, so it's definitely worthwhile to look over the board again to ensure nothing else it out of place. In case you have not already seen it I strongly suggest going over the Schematic Checklist. It's by no means comprehensive, but it's a good start.

    I don't have IAR so I have no idea what that code is doing, but in my experience your symptoms fall into one of those two categories. The AM335x has been around for a while and a lot of folks have been successful in using it, so once you narrow down the root cause I am confident you will be able to get it up and running as well.

  • A Starterware example that I tried was:
    C:\ti\AM335X_StarterWare_02_00_00_07\examples\evmskAM335x\gpio_card_detect\gpioCardDetect.c
    I cut it down to just the first three function calls in main(). However, these
    examples never even get to main(); they lock up --I have to click to stop
    execution-- on a branch instruction beforehand.

    A semi-trivial example that contains only some variable incrementing and a
    relative test was hanging on a CMP R0,R2 instruction. Then later it wasn't.

    I agree that it seems hard to believe that even the experimental silicon would
    lock up on instructions. It is verrrrrry innnnnteresting that after a while the
    instructions changed on which I got hangs.

    I can keep in mind trying an eval kit with the same level processor, an AM3359
    rather than an AM3358.

    I have been looking at my compiler settings. .intvec start is 0x402F0400, ROM is
    0x402F0400 to 0x40307FFF, RAM is 0x40308000 to 0x4030FFFF, and
    Stack/Heap Sizes are:
    CSTACK 0x1200, SVC_STACK 0x40, IRQ_STACK 0x100, FIQ_STACK 0x40, UND_STACK 0x40,
    ABT_STACK 0x40, HEAP 0x400.

    In the memory map in the spruh73i.pdf userguide or TRM, this crosses the "ROM"
    over from SRAM internal to L3 OCMC0. Could that cause a problem? The L3 OCMC0 is
    described as "32-bit Ex/RW OCMC SRAM". I'll have to read more about that.

    For an FAE for me, I wonder if someone can find me a reference or a link to
    select one? I am located in Charlottetown, PEI, Canada. Today in Canada we just
    use two-letter abbreviations for the provinces, so we just write "PE" instead of
    "PEI".

  • I have been able to find little information about the L3 OCMC0. It is listed as being from 0x40300000 to 0x4030FFFF in the TRM. Does it require any initialization or can it be relied on automatically just like the internal SRAM just below it? Since the internal SRAM is 64-1kB and the L3 OCMC0 is 64kB, does that mean that the internal RAM of the AM335x is 128-1 = 127 kB? That first kB is Reserved.


  • I changed my memory plan to use only the SRAM internal and to stay out of the
    L3 OCMC0, and code execution now gets through the PUSH {R7, LR} instruction.
    So what needs to be working or initialized to get the 64 kB of L3 OCMC0 going?
    What kind of problems can stop it? Is there actually 64 kB of physical memory on
    the chip for that 0x4030 0000 - 0x4030 FFFF, as per the TRM?

  • Yes, there's an L3 RAM. The StarterWare examples do function as-is on the eval boards. It does require a clock and power, both of which the GEL file usually sets up. If you are not using a GEL file (this is a CCS configuration "script") or the equivalent in IAR then the likely issue is that your memory does not have a clock and/or power.