IPNCRDK 3.5, Memory Cache configuration

chinghok Tse

Hi TI,

On IPNCRDK3.5, the SR0 (Syslink MsgQ / IPC List MP) and SR2 (Frame buffer) is non-cached, while SR1 (Bitstream buffer) is cached. How and where do the cache configuration done?

Regards,

ChingHok

over 12 years ago

0 Rajat Sagar over 12 years ago

TI__Expert 8780 points

The upper 512M ddr section is cached.

Check the AMMU_m3.cfg file to check the caching policy for M3s.

Regards

Rajat

0 chinghok Tse over 12 years ago in reply to Rajat Sagar

Prodigy 150 points

Hi Rajat,

If the upper 512M DDR is cached, why on 256M configuration, SR1 is said to be cached and SR0 is said to be non-cached? They suppose in the similar memory range. (in config_256M.bld)

Regards,

ChingHok

0 Rajat Sagar over 12 years ago in reply to chinghok Tse

TI__Expert 8780 points

ChingHok, The upper 512MB is refereed from 0x80000000-0xA0000000 (512MB).

As you can refer in the memory map SR1 & SR2/SR0 are in different sections.

Regards

Rajat

Processors

Processors forum

IPNCRDK 3.5, Memory Cache configuration