• State
  • Locked Locked
  • Replies 5 replies
  • Subscribers 99 subscribers
  • Views 687 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

AM335x DDR3 Phy values

Arno Morbach
Prodigy 90 points

TI offers the DDR3_slave_ratio_search_auto.zip tool for setting the DDR PHY registers. But I can find no information how the tool works. How do I know about the safety margins for the acquired values? We would like to use the microprocessor in a medical device but I don't want to rely on a tool which might not fulfill the necessary quality requirements. Are there sources available?

  • 0
    TI__Intellectual 2325 points

    Hi Arno,

    Please have a look at this links on our WIKI page4657.DDR3 Software Leveling and Registers Configuration.pdf and the presentation attached.

    http://processors.wiki.ti.com/index.php/AM335x_EMIF_Configuration_tips

    You will find some more information on these pages related to memory interface set-up of the AM335x devices. Please let me know if you need more.

    Best Regards

    Jens Stapelfeldt

  • 0 in reply to Jens96
    Prodigy 90 points

    Hi.

    The first link was new to me, but it also does not really describe what the calc tool really does. Is it right, that the spreadsheet tool determines the seed values which initially should work. After that the DDR3_slave_ratio_search_auto.out changes these values and checks for proper data values by reading and writing DDR data to optimize the settings? I would like to know more about the used algorithm.

    Regards

    Arno Morbach

  • 0 in reply to Arno Morbach
    TI__Intellectual 1570 points

    "- I would like to know more about the used algorithm."

    Me too

    /Stefan

  • 0 in reply to Bob Hund
    Prodigy 90 points

    I'm still waiting for more information about the algorithm. Isn't there someone at TI who knows about the internals of this software or is TI not willing to publish this information?

    Regards

    Arno Morbach

  • 0 in reply to Arno Morbach
    TI__Genius 9655 points

    Arno

    Basically, the leveling program accomplishes the following after the initial settings that enable a basic READ/WRITE to the external DDR. All the required settings to accomplish a basic READ/WRITE are documented in the link that was referred to above.

    There are 3 different tasks the leveling program performs. I'm listing them below:

    Write Leveling:

    As part of this, the software program positions the DQS w.r.t. Clock and identifies a passing window as the DQS is swept w.r.t. clock. After identifying the min. and max. passing window, it reports the DQS position such that it is at the center of the passing window to ensure the best margin.

    Read Leveling:

    As part of this, the software program positions the DQS w.r.t. Data and identifies a passing window as the DQS is swept w.r.t incoming DQ. After identifying the min. and max. passing window, it reports the Read DQS position such that it is at the center of the passing window to ensure best margin.

    Read Gate Training:

    The read data is captured in an internal FIFO which is controlled by the incoming DQS. For the FIFO to work correctly, the DQS should be gated during READ-WRITE and WRITE-READ turn around since the DQS is bi-directional. The idea of Read Gate Training is to make sure the internal DQS is enabled and disabled correctly in the preamble and post-amble times of the read DQS. The software program here positions the DQS gate w.r.t. incoming DQS as the DQS gate is swept w.r.t incoming DQS. After identifying the min. and max. passing window, it reports the DQS gate position such that it is at the center of the passing window to ensure best margin.

    If you have any further queries, please contact your local FAE and we can work with you to provide any further information.

    Regards, Siva