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SMBUS on AM3730

Vishnu Patekar
Prodigy 50 points

Hello,

We are using AM3730.

We’ve a battery charger(LTC4100) which communicates over SMBUS(I2C3 port). 

As per SMBUS spec 1.1, Slave can hold the clock low till it is ready to respond.

Is I2C clock stretching is supported in AM3730? If Yes, How?, Do we need to do specific configurations in I2C for that?

Does AM3730 wince/linux driver supports smbus commands?

When AM3730 tries to communicate LTC4100 charger i.e. 0x9. It seems, it tries to ACK, however, At the 9th clock data and clock is not proper. Please find the waveform as below.

 

  • 0
    TI__Intellectual 1340 points

    Hi Vishnu,

    According to your questions about I2C clocking I think AM37x devices I2C modules support Clock stretching by default (built in function) as mentioned in TRM p2781 section 17.2.1.3.10 HS I2C Clock Generation and Synchronization.

    Are you achieve some successful communication between AM3730 and the LTC4100?

    To what voltage are connected the external pull up resistors? 

    I can't answer the SMBUS driver related question unfortunately. Also for SW feature support question you have to mention the exact SW release version you use.

    Best regards,

    Vidin

  • 0 in reply to Vidin Tsonev-XID
    Prodigy 50 points

    Hello Vidin,

    Thanks for the response.

    please find the diagram as below: host side 4.08K (1.8V)pull-upsand on LTC4100 side 15K(5V) pull-ups are there.

    When AM3730 tries to communicate LTC4100 charger i.e. 0x9. It seems, it tries to ACK, however, At the 9th clock data and clock is not proper. Please find the waveform as attachment:

    Regards,

    Vishnu

  • 0 in reply to Vishnu Patekar
    TI__Intellectual 1340 points

    Hi Vishnu,

    On first look the schematic looks OK.

    One note can you try to change the 5V side pull ups to 4.7kohm as the 15kohm supply to low current and the rise and fall times could be affected. (this depends on the LTC4100 internal buffer design which we do not know:))

    I cannot read the part number of the level shifter. Can you post it?

    And at which side the timing diagrams were taken 1.8V or 5V?

    I will check some other possible isues based on AM335x I2C setup.

    BR,

    Vidin

  • 0 in reply to Vidin Tsonev-XID
    Prodigy 50 points

    Hi Vidin,

    Level shifter part no is TXS0102DCTR.

    Timing diagram were taken at slave side i.e. 5V.

    One update is we were successfully able to communicate to RTC on I2C3 with same level shifter, same frequency, we connected RTC just for testing.

    Regards,

    Vishnu

  • 0 in reply to Vishnu Patekar
    TI__Intellectual 1340 points

    Hi Vishnu,

    I checked the SMBUS specs and LTC4100 datasheet and it seems that your settings are Ok. I think the problem is with LTC4100 responce to I2C write.

    First can you try to write to LTC4100 its slave address (0x12 I think, please check again). According to spec all communication to LTC4100 must start with this address byte first in 7 bit mode and one bit R/W data. 

    Also you can slow down the AM3x I2C clock a little bit more as the SMBUS is slower interface and some rise and fall pulse timing can be an issue when interfacing standard I2C.

    I think AM3x I2C works correctly as you were able to communicate with RTC fine.

    BR,

    Vidin