Hi,
I have a customer with a C5505 device and is GPIO[21-26] pins instead of using the EMIF pins within the submodule. Still these pins are supplied from DV_DDEMIF. The customer is looking at reference designs with 9 .1uF (one per supply pin) and a 10uF bulk cap.
I've looked through the data sheet and at the processor wiki site about BGA decoupling [1] and can't find anything other than general guidelines. The customer is not using EMIF (which is being used in his reference design) and wants to know if he can remove some of the caps because he is only supplying 6 GPIO pins. I've also communicated that if he can use other GPIO pins he doesn't need to even use the EMIF module but he does not have any spare GPIO pins.
Can anyone give me more specific information about a possible minimum number of caps for the EMIF submodule?
Thanks,
Matt