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C6748's UPP multi lines

Giora Shenitzer
Prodigy 80 points
Other Parts Discussed in Thread: TMS320C6748

Hello,

1. I'm using the uPP at 50Mhz, when line is changed data is lost.

2. With relative big line buffer >= 32KB and 35 lines, only 1st line is miningfull

   the address at destination (UPQS0) is less then source (UPQD0) and got error bits set, 0x3C at UPISR

3. when I poll the bytes count (UPQS1 LS16), they changed before data is in memory.

(sorry about the spelling, the spell check didn't worked :) )

any suggestions ?

Thanks

G. shenitzer

  • 0
    TI__Mastermind 20790 points

    Shenitzer,

    Welcome to the TI E2E forum. I hope you will find many good answers here
    In addition you can find some details through the TI.com documents and the TI Wiki Pages.
    Be sure to search those for helpful information and to browse for the questions others may have asked on similar topics.

    Please clarify the mode of operation used for UPP.
    UPQS0:
    This register is read only and reports the current address of the DMA ChannelQ transfer.

    UPQD0:
    This register have three lower bits are read-only and always equal to 0 and data buffers must be
    properly aligned in memory.

    UPISR:
    Disabled events do not generate interrupts but do assert bits in the interrupt raw status register (UPISR).

    In addition that, refer the below wiki pages for UPP pheriperal
    http://processors.wiki.ti.com/index.php/Introduction_to_uPP
    http://processors.wiki.ti.com/index.php/Using_the_uPP_DSP/BIOS_Driver

    Go to LogicPD's web site. Click on the Kit Contents tab, at the bottom of the page click at:
    TMS320C6748 SOM-M1 GEL, CCS Setup, & BSL Files - you will need to create an account in their website if you do not have one already and download the files.
    The basic upp example will be at: evmc6748_v1-1\tests\evm\upp