McBSP driver

Chris Roed

Intellectual 960 points

Other Parts Discussed in Thread: ADS1274, SYSBIOS

Hello, We're having some trouble setting up the McBSP clocks with BIOS psp drivers

versions

CCS 5.4

SYS/BIOS 6.35.3.47

EDMA3 2.11.4

BIOSPSP 3.00.01.00

XDC 3.25.2.70

C6748 LCDK (modified gel file to run at 456Mhz, DDR2 at 150Mhz)

We started with the McBSP DLB example, and we've been modifying it for use with an ADS1274 ADC. We've gotten to the point where we've disabled the Tx, and gotten the Rx module to generate a clock and a framesync signal, but we can't seem to figure out how to set the clock speeds correctly. From the alpha code version (C6748 starterware, no RTOS) we know that CLKR should be ~33Mhz, and FSR should be ~124Khz.

The only clock speed references I can find in the McBSP driver are

mcbspSrgParams.srgrInputFreq = 150000000; and

Mcbsp_ClkSetup mcbspClkConfigRx =
{
Mcbsp_FsClkMode_INTERNAL,
96000, /* 96KHz */
Mcbsp_TxRxClkMode_INTERNAL,
Mcbsp_FsPol_ACTIVE_HIGH,
Mcbsp_ClkPol_FALLING_EDGE
};

I can modify the input frequency and the 96000 just fine, but they seem to be dependent on one another, and modifying the 96000 will change the CLKG speed. So... we've found the code to tell the driver what the input clock speed is...how do you tell the driver what you want to output clock speed to be? Previously, I was using the startware to manually set CLKGDIV and FPER.

over 12 years ago

0 Chris Roed over 12 years ago

Intellectual 960 points

I've been doing some more searching here, and I've found some interesting things...

For my application, I need the CLKR to be 33MHz, and the FSR to be at 124KHz, both generated by the DSP. Each FSR, I want to read a single 24 bit value.

After playing a bit more with the driver, I'm not sure this is even possible.

Using the driver to set McBSP_WORDLENGTH_24 not only sets my word length at 24 bits, it sets the FPER to 24 bits. The CLKGDIV seems to be set by both the SRGR input frequency, and the read frequency I set in the Mcbsp_Clksetup

I tried using the HWREG macro to manually set the SRGR register after I call GIO_Create(), but that didn't work... I assume that the driver locks the registers.\

Is there any way to accomplish what I'm trying to do in SYSBIOS?

0 Raja over 12 years ago in reply to Chris Roed

TI__Guru* 81335 points

Hi Chris Roed,

Thanks for the post.

To operate the McBSP with internal frequency update the Mcbsp_srgConfig as follows:

static Mcbsp_srgConfig mcbspSrgCfg =
{
FALSE, /* No gsync to be used as input is not CLKS */
Mcbsp_ClkSPol_RISING_EDGE, /* Dont care as input clock is not clks */
Mcbsp_SrgClk_CLKCPU, /* McBSP internal clock to be used */
150000000, /* Mcbsp internal clock frequency */
0 /* frame sync pulse width (val+1) is used */
};

Please refer the mcbspSampleMaster example which uses internal clock for transmit.

Migrating a DSP/BIOS application to SYS/BIOS application is possible. Please refer the below wiki link and Application report(SPRAAS7).

http://processors.wiki.ti.com/index.php/Differences_Between_DSP/BIOS_and_SYS/BIOS

http://processors.wiki.ti.com/index.php/Category:SYSBIOS

0 Raja over 12 years ago in reply to Raja

TI__Guru* 81335 points

Hi Chris,

CLKG has a frequency equal to 1/(CLKGDV + 1) of the sample rate generator input clock. Thus, the
sample rate generator input clock frequency is divided by a value between 1 to 256.

Note: The CLKGDV value chosen must result in a clock that meets the timing requirements/limitations specified in the device-specific data manual.

The clkgDiv, framePeriod variables in function Mcbsp_localConfigureSrgr() configures the clocks i.e. sample rate generator(CLKG) and frame sync generator(FSG).

I have following queries.

What is the McBSP internal clock frequency?

Is it possible to check with the CLKR source as per the example mcbspSampleSlave?

Thanks.

0 Chris Roed over 12 years ago in reply to Raja

Intellectual 960 points

Hi Rajasekaran,

I have already updated the Mcbsp_srgConfig as you have shown. The Mcbsp_Object contains the SRGR object, but there's no actual information in the Srgr object that lets me set the clkgdiv and fper. The only think that affects the clock div is changing the input frequency field.

I'm looking at the function:

Int32 Mcbsp_localConfigureSrgr(Mcbsp_Object *instHandle, Mcbsp_ChannelObj *chanHandle).

Inside the function there is the line 2536

clkgDiv = ((instHandle->srgrConfig.srgrInputFreq/(chanHandle->clkSetup.samplingRate* noOfBits)) - 1u);

framePeriod = (noOfBits - 1u);

That is my problem. The driver forces me to have a frame period of my wordlength - 1. This will not work for me. Can I modify and rebuild the driver libraries? or just include the source code?

0 Raja over 12 years ago in reply to Chris Roed

TI__Guru* 81335 points

Hi Chris Roed,

Thanks for the post.

From my understanding, the Frame Period duration will be decided by Word length and Frame Length.

May be you shall try to modify and rebuild the driver libraries.

Note:

The Frame Period (FPER bits) in the sample rate generator register (SRGR) are a 12-bit down-counter that can count down the generated data clocks from 4095 to 0.

Make sure that the FPER value should be greater than (noOfBits - 1u) and less than 4095 to avoid overlap.

Please refer the TRM(SPRUH77), Section 26.2.5.4.1 Frame Period (FPER) and Frame Width (FWID) for more details.

Please refer the section 26.2.7.1 Receive Operation for receive timing diagram of McBSP.

0 Chris Roed over 12 years ago in reply to Raja

Intellectual 960 points

Rajasekaran,

Thanks for the info. I got the McBSP working on my alpha version of code using the C6748 starterware, so I have an idea of what I need to do.

I'm thinking about how to best modify the driver... My first thought is that I should add another field to the Mcbsp_srgConfig called srgrOutputFreq. Then, inside the Int32 Mcbsp_localConfigureSrgr() function, I will modify the clk settings such that

clkgDiv = ((instHandle->srgrConfig.srgrInputFreq/(intHandle->srgrConfig.srgrOutputFreq) - 1u);

framePeriod = (instHandle->srgrConfig.srgrOutputFreq/chanHandle->clkSetup.samplingRate - 1u);

I think that should work. Please let me know if you see anything glaringly wrong.

0 Chris Roed over 12 years ago in reply to Chris Roed

Intellectual 960 points

This is what I did to get the clock working.

1. Remove references to mcbsp driver library in the CCS project link files.

2. included the three mcbsp source files into the project (I will rebuild the libraries later, this seems easier for debug) I also changed the include file paths for mcbsp.h and mcbsplocal.h

3. in mcbsp.h typedef of Mcbsp_srgConfig_t I added Uint32 srgrOutputFreq;

4. in mcbsp.c declaration of srgConfig, make the same change

5. in mcbsp.c functio nMcbsp_localConfigureSrgr(), (line 2536)

clkgDiv = ((instHandle->srgrConfig.srgrInputFreq/(intHandle->srgrConfig.srgrOutputFreq) - 1u);

framePeriod = (instHandle->srgrConfig.srgrOutputFreq/chanHandle->clkSetup.samplingRate - 1u);

the method I used above worked pretty well, however I did have some rounding issues... CLKGDIV was computed as 5.9ish and rounded to 5 because that's how the integers do.

I just increased my output frequency until clkgdiv came out as 6.

Also something to keep in mind if you're going to make these mods... the default mcbsp clock is sysclock/2. My sysclock is 456MHz, so I changed my input freq to 228MHz. You can change where the mcbsp gets it's clock... it's all in the C6748 technical reference manual.

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