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Not sure design guide recommendations exist?

TI Lady
Genius 4025 points

My question is that the Keystone hardware design guide has minimum decoupling requirements for all the rails but the eval card does not follow this and has much less than the guide advises, why? The guide advises to use 470uF caps with max ESR of 12mOhm and we are not sure these exist.  This is for the

TI TMDSEVM6657LS

Also, When using a single DDR3 device with the C6657, is end termination advised for the address and control lines?

Please advise.

Thanks!!

  • 0
    TI__Genius 13045 points

    Note that EVMs are not necessarily reference designs which should be used for production layouts.  When there is conflict between Datasheet/Design Guides and EVM implementation, follow the documentation specifications. EVMs are designed before final silicon is available many times, so all implementation constraints haven't been deteremined yet.

    Not sure on the termination question.  I didn't see anything in the Design Guide terminations which suggested using different rules for single vs multiple DDR3 devices.  Will need to check with Design team.

    Regards.

  • 0 in reply to TommyG
    Genius 4025 points

    Hi  there, 
    Thanks,

    please can someone advise me then of a 470uF 12mOhm capacitor as required by the TI design guides? I failed to find one. 

    Thanks,

  • 0 in reply to TI Lady
    TI__Mastermind 46460 points

    The KeyStone Hardware Design contains decoupling guidance for all KeyStone-1 devices.  Unfortunately, this guidance does not scale for device power.  For instance, the C6657 is much smaller than the C6678 and this guidance is for both.  In this case, the EVM content is sufficient.  We are working to develop a better method of determining the optimum number of decoupling for a given board design but this is not available yet.

    Bulk capacitors such as a 470uF 12mOhm cap can be made up of multiple caps in parallel if the exact value can be found.  The capacitance adds when in parallel.  The ESR divides just like parallel resistors.  You simply need to find a combination that adds up to no less than 470uF and has an ESR no greater than 12 mOhms.

    Address, command, control and clock DDR3 routing for KeyStone devices is always routed in a fly-by topology as defined in the JEDEC spec.  This topology always has resistors to VTT at the ends of the address, commandf and control nets.  Clock nets have a differential AC termination to VTT.

    Tom

     

  • 0 in reply to Tom Johnson 16214
    TI__Genius 12790 points

    Tom,

    I have similar question wrt providing enough bulk capacitance for a lower power C6657 (dual core).  In HW Design Guide, page 25, CVDD recommends 1663uF minimum for 10W solution.

    If customer is going to be ~3.5-4W, can you do a simple calculation of [4/10 * 1663] = 665.2uF?

    If this does not apply, can you suggest how to adjust the min, bulk capacitance for ~3.5W C6657 design.

    Thanks. Marc

  • 0 in reply to pathfinder
    TI__Mastermind 46460 points

    Marc,

    Restating what i said above:

    The KeyStone Hardware Design contains decoupling guidance for all KeyStone-1 devices.  Unfortunately, this guidance does not scale for device power.  For instance, the C6657 is much smaller than the C6678 and this guidance is for both.  In this case, the C6657 EVM content is sufficient.  We are working to develop a better method of determining the optimum number of decoupling for a given board design but this is not available yet.

    Tom