CSL library for c6678

Hi,

In <pdk_dir>/docs you should find a RelaseNotes_CLS.pdf file wth the list and names of the included library, that should be under the directory <pdk_dir>/packages/ti/csl/build:

• ti.csl.ae66: C66 ELF Little Endian Library
• ti.csl.ae66e:  C66 ELF Big Endian Library
• ti.csl.intc.ae66: C 66 ELF Interrupt Controller Little Endian
• ti.csl.intc.ae66e: C66 ELF Interrupt Controller Big Endian

In my release the COFF version is not included (deprecated).

Somnath,

They're in the directory you indicated for that version.  I believe what's confusing you is the extension has changed.

It's now .ae66 (little endian) and .ae66e (big endian.)

Here's a link to a thread that goes into the differences.

Best Regards,

Chad

Thanks.

Somnath

I only see docs (ReleaseNotes) for CPPI_LLD, HYPLNK_LLD, PA_LLD etc.

There is also ReleaseNotes_PDK but don't see the CSL doc.

We have been using .lib and generating COFF .out file. Do we need to switch to ELF format for our .out then?

In our case, the .out file goes through another internal tool of ours to convert to .rbv files that get built with the CPU files. 

Looks like all the libraries now support only elf format. We use dsplib, imglib and mathlib.

Can we still generate COFF formatted output (.out file) or it will only generate ELF formatted output.

You'll want to use ELF format.

Best Regards,

Chad

Interestingly this is what I found from IMGLIB user manual - it supports both COFF and ELF but only little endian.

However the DSPLib supports both COFF and ELF and Little and Big endian

Somnath

Here is a big issue I am facing now.

We developed the full system on c6472 and used the CSL layer to build our EDMA layer (with APIs for the app layer).

Now when I brought in c6678 CSL, the compile fails because

these files are missing - cslr_dev.h and cslr_edma3cc.h

the following were defined in cslr_edma3cc.h that we use

#define CSL_EDMA3CC_DRAE_E31_MASK (0x80000000u)
#define CSL_EDMA3CC_DRAE_E31_SHIFT (0x0000001Fu)
#define CSL_EDMA3CC_DRAE_E31_RESETVAL (0x00000000u)

. . .

#define CSL_EDMA3CC_DRAE_E1_MASK (0x00000002u)
#define CSL_EDMA3CC_DRAE_E1_SHIFT (0x00000001u)
#define CSL_EDMA3CC_DRAE_E1_RESETVAL (0x00000000u)

#define CSL_EDMA3CC_DRAE_E0_MASK (0x00000001u)
#define CSL_EDMA3CC_DRAE_E0_SHIFT (0x00000000u)
#define CSL_EDMA3CC_DRAE_E0_RESETVAL (0x00000000u)

It is complaining about

CSL_EDMA3_DMACHANNELSETUP_DEFAULT and likes.

CSL_EDMA3_DMACHANNELSETUP_DEFAULT was previously defined in csl_edma3.h

Any help?

 Thanks,

SBanik

Hi Somnath,

thanks for posting this on e2e. As we have noticed the cslr register level CSL has been removed. We are now looking at two options:

(1) Use the CSL API at C:\TI\pdk_C6678_1_1_2_5\packages\ti\csl\src\ip\edma

(2) Use the EDMA LLD

Somnath, since you have existing code that was based on the previous CSLR, could you post some example code that you are looking at needing to get ported, in order to show the type of port. We understand you implemented your own EDMA helper functions on top of CSLR and need to migrate that to the new CSL

Maybe someone can make a recommendation of whether it is better to use the CSL API or the EDMA LLD. As we have said the LLD offers advantages in resource management as well as in long term support for Keystone devices.

But again it may be a matter of how your functions migrate best to the new CSL API.

Regards,

--Gunter

Gunter,

Thanks for taking this up.

Here are some examples -- 

1) func: Edma_rawTransfer(..)

EDMA_Status Edma_rawTransfer(EDMA_LogicalBaseChan logCh, EDMA_TransferParams *pTransferParams)
{
Edma_ChInfo *edmaChInfo;
int phyCh;
int coreId = MultiProc_self();

edmaChInfo = &gEdmaCoreInfoLkup[coreId][gEdmaChanAssignment[logCh].logChToCoreCh[coreId]];
phyCh = edmaChInfo->phyCh;
volatile CSL_Edma3ccParamsetRegs *param = &((CSL_Edma3ccRegsOvly) CSL_EDMA3CC_0_REGS)->PARAMSET[phyCh];
Uint32 ABSyncFlag = (pTransferParams->isABSync) ?
CSL_FMKT(EDMA3CC_OPT_SYNCDIM, ABSYNC) : CSL_FMKT(EDMA3CC_OPT_SYNCDIM, ASYNC);

ErrorMgr_assertFatal(!edmaChInfo->pending, ERROR_TYPE_HW_MGR_EDMA3_CHAN_IN_USE, (int)logCh);

// set up OPT register
param->OPT = (pTransferParams->CCnt > 1) ?
// chained transfer
ABSyncFlag |
CSL_FMKT(EDMA3CC_OPT_TCINTEN, ENABLE) |
CSL_FMKT(EDMA3CC_OPT_ITCCHEN, ENABLE) |
CSL_FMK (EDMA3CC_OPT_TCC, phyCh) |
CSL_FMKT(EDMA3CC_OPT_STATIC, NORMAL) :
// normal transfer
ABSyncFlag |
CSL_FMKT(EDMA3CC_OPT_TCINTEN, ENABLE) |
CSL_FMK (EDMA3CC_OPT_TCC, phyCh) |
CSL_FMKT(EDMA3CC_OPT_STATIC, STATIC);

// src and dst address
param->SRC = (Uint32)SpDsp_local2GlobalAddr(pTransferParams->pSrc, MultiProc_self());
param->DST = (Uint32)SpDsp_local2GlobalAddr(pTransferParams->pDst, MultiProc_self());

// ACnt, BCnt, CCnt
param->A_B_CNT = CSL_FMK(EDMA3CC_A_B_CNT_ACNT, pTransferParams->ACnt) |
CSL_FMK(EDMA3CC_A_B_CNT_BCNT, pTransferParams->BCnt);
param->CCNT = CSL_FMK(EDMA3CC_CCNT_CCNT, pTransferParams->CCnt);

// BIdx and CIdx
param->SRC_DST_BIDX = CSL_FMK(EDMA3CC_SRC_DST_BIDX_DSTBIDX, pTransferParams->dstBIdx) |
CSL_FMK(EDMA3CC_SRC_DST_BIDX_SRCBIDX, pTransferParams->srcBIdx);
param->SRC_DST_CIDX = CSL_FMK(EDMA3CC_SRC_DST_CIDX_DSTCIDX, pTransferParams->dstCIdx) |
CSL_FMK(EDMA3CC_SRC_DST_CIDX_SRCCIDX, pTransferParams->srcCIdx);

// for A-Sync case, BCNT must be reloaded between C runs. The controller makes us set the reload
// register value here. This seems like an inefficient design, since we can't imagine what might possess
// someone to set BCNTRLD to anything other than the original BCNT, but we have to trust that there's some
// inner architectural reason for it.

// BCNTRLD is only used (and required) by A-Sync transfers, but is ignored otherwise, so we set it here regardless
// of the sync mode. This factoid is in spru727d/Section 2.3.2.7.
param->LINK_BCNTRLD =
CSL_FMK(EDMA3CC_LINK_BCNTRLD_LINK, 0xFFFF) |
CSL_FMK(EDMA3CC_LINK_BCNTRLD_BCNTRLD, pTransferParams->BCnt);

// trigger the transfer
{
Uint32 cs = _disable_interrupts();
if (phyCh < 32)
{
((CSL_Edma3ccRegsOvly) CSL_EDMA3CC_0_REGS)->ESR = (1 << phyCh);
}
else
{
((CSL_Edma3ccRegsOvly) CSL_EDMA3CC_0_REGS)->ESRH = (1 << (phyCh - 32));
}
_restore_interrupts(cs);
}

// housekeeping
edmaChInfo->waitCount = 0;
edmaChInfo->pending = TRUE;

Cache_wb(edmaChInfo, sizeof(Edma_ChInfo), Cache_Type_ALL, TRUE);

return EDMA_SUCCESS;
}

2) func: Edma_copy(..)

EDMA_Status Edma_copy(EDMA_LogicalBaseChan ch,
void *pSrc,
void *pDst,
Int32 nElements,
Int32 szElements,
Int32 nLines,
Int32 pitchSrc,
Int32 pitchDst)
{
EDMA_TransferParams transferParam =
// pSrc, pDst, isABSync, ACnt, BCnt, CCnt, srcBIdx, dstBIdx, srcCIdx, dstCIdx
{ NULL, NULL, 0, 0, 0, 1, 0, 0, 0, 0 };

transferParam.pSrc = SpDsp_local2GlobalAddr(pSrc, MultiProc_self());
transferParam.pDst = SpDsp_local2GlobalAddr(pDst, MultiProc_self());
transferParam.ACnt = nElements * szElements;
transferParam.BCnt = nLines;

if (nLines != 1) // 2D to 2D copy
{
transferParam.isABSync = 1;
transferParam.srcBIdx = pitchSrc * szElements;
transferParam.dstBIdx = pitchDst * szElements;
}
return Edma_rawTransfer(ch, &transferParam);
}

3) func: HwMgr_edma3Init()

void HwMgr_edma3Init()
{
CSL_Edma3HwSetup hwSetup;
CSL_Edma3HwDmaChannelSetup dmahwSetup[CSL_EDMA3_NUM_DMACH] = \
CSL_EDMA3_DMACHANNELSETUP_DEFAULT;

CSL_Edma3Obj edmaObj;
CSL_Edma3Handle hModule;
CSL_Edma3CmdIntr regionIntr;
CSL_Edma3CmdDrae regionAccess;
// CSL_Edma3ChannelHandle hChannel;
// CSL_Edma3ChannelAttr chAttr;
CSL_Edma3Context context;
CSL_Status status;

/* Module Initialization */
status = CSL_edma3Init(&context);
if (status != CSL_SOK) {
// printf ("Edma module initialization failed\n");
return;
}

/* Module level open */
//SNB was like this in c6472 hModule = CSL_edma3Open(&edmaObj,CSL_EDMA3,NULL,&status);
hModule = CSL_edma3Open(&edmaObj,EDMA3_CC1,NULL,&status);
if ( (hModule == NULL) || (status != CSL_SOK)) {
// printf ("Edma module open failed\n");
return;
}

//module setup
hwSetup.dmaChaSetup = &dmahwSetup[0];
hwSetup.qdmaChaSetup = NULL;
status = CSL_edma3HwSetup(hModule,&hwSetup);
if (status != CSL_SOK) {
// printf ("Hardware setup failed\n");
CSL_edma3Close (hModule);
return;
}

/* DRAE enable(Bits 0-15) for the shadow region 5 */
regionAccess.region = CSL_EDMA3_REGION_2 ;
regionAccess.drae = CSL_EDMA3CC_DRAE_E0_MASK|CSL_EDMA3CC_DRAE_E1_MASK|CSL_EDMA3CC_DRAE_E2_MASK|CSL_EDMA3CC_DRAE_E3_MASK|
CSL_EDMA3CC_DRAE_E4_MASK|CSL_EDMA3CC_DRAE_E5_MASK|CSL_EDMA3CC_DRAE_E6_MASK|CSL_EDMA3CC_DRAE_E7_MASK|
CSL_EDMA3CC_DRAE_E8_MASK|CSL_EDMA3CC_DRAE_E9_MASK|CSL_EDMA3CC_DRAE_E10_MASK|CSL_EDMA3CC_DRAE_E11_MASK;
regionAccess.draeh = 0x0000 ;
status = CSL_edma3HwControl(hModule,CSL_EDMA3_CMD_DMAREGION_ENABLE, \
&regionAccess);
if (status != CSL_SOK) {
// printf ("Edma region enable command failed\n");
return;
}

/* Interrupt enable (Bits 0-11) for the shadow region 5 */
regionIntr.region = CSL_EDMA3_REGION_2 ;
regionIntr.intr = 0x0003; //changed from 0xFFF to 0x0003 SNB 5-17 ;
regionIntr.intrh = 0x0000 ;
status = CSL_edma3HwControl(hModule,CSL_EDMA3_CMD_INTR_ENABLE, &regionIntr);
if (status != CSL_SOK) {
// printf ("Edma interrupts enable command failed\n");
return;
}

// initialize all EDMA channels to UNUSED
Edma_allChannelClose();
}

I also need some help with some questions regarding the EDMA example in 

pdk_c6678_1_1_2_6\packages\ti\csl\examples\edma\edma_test.c

lines 703-707

/* Interrupt enable (Bits 0-11) for the shadow region 5 */
regionIntr.region = regionNum;
regionIntr.intr = 0x0FFF;
regionIntr.intrh = 0x0000;
if (CSL_edma3HwControl(hModule,CSL_EDMA3_CMD_INTR_ENABLE, &regionIntr) != CSL_SOK)

{...}

Q1. region 5 in the comment is possibly typo - correct?

Q2. channel number is passed to this function as a parameter and the lines preceding these lines sets up DRAE as  regionAccess.drae   = 0xFFFFFFFF;

Why then is interrupt enable only 0-11? Why is it not 0-31 or just the channel number that was passed?

How is hard coded value 0xFFF derived in setting

regionIntr.intr = 0x0FFF;  (line 705)?

- Somnath Banik