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TMS320c6678 PCIe multi-lane

Bruno B
Expert 1290 points

Hi,

I have some question about PCIe in multi-lane mode.

We can read in the serdes implementation guide SPRABC1 (page 21 § 7.2)  some skew recommandations when using multi lane communication : "Both complementary PCIe receive pairs PCIERXN/P1:0 shall be assigned to an individual net class where routing skew shall not be greater than 5 ps between all receive pairs"

It is also said §7.1 : "The PCIe interface on KeyStone I devices is compliant with Physical Layer Specifications referenced in Chapter 4 of the PCI Express Base Specification Revision 2.0."

However the PCIe base specification 2.0 defines (chapter 4 : Physical layer specification)  the L-Rx-skew (maximum lane-to-lane skew at the receiver input) to be 8ns when running links at 5Gb/s.

1)  Why do you request 5ps max skew between lane at the DSP receiver side ?

2) The PCIe specification also defines the L-TX-skew (lane-to-lane output skew) that should respect the DSP on the transmitter side (silicon characteristic I guess). That max value is 500ps+4*U.I .(big value) I interpret this as a tolerance that is given to the transmitter.

==> what is the DSP driver characteristic in term of L_TX-skew ?

==> Given that the transmitter may introduce such a large amount of skew beetwen 2 lanes, why again request a 5ps skew at the receiver side ?

Did I understood something wrong ?

With best regards,

BRuno

  • 0
    TI__Mastermind 42545 points

    Hi Bruno,

    The error in the skew requirements was found while preparing the document for the KeyStone II devices and fixed in that document. These changes will be back filled into the KSI document but, for now, you can reference the routing requirements in section 8.2 of the KSII document.

    http://www.ti.com/lit/ug/spruho3/spruho3.pdf

    Regards, Bill

  • 0 in reply to Bill Taboada
    Expert 1290 points

    Hi Bill,

    - OK, we then refer to the SPRUHO3 document for PCIe routing constraint.

    - Does this guide also apply for SRIO and SGMII constraint, or should we still stick to the SPRABC1 for these interfaces ?

    Thanks for your help,

    Bruno

  • 0 in reply to Bruno B
    TI__Mastermind 42545 points

    Hi Bruno,

    There were some changes made to SRIO and SGMII. I would use the KSII document for those interfaces as well.

    Regards, Bill

  • 0 in reply to Bill Taboada
    Expert 1290 points

    Hi Bill,

    I am still worried by this new PCIe Keystone II specification.

    It is explained that the Rx lane-to-lane skew should be less than 2UI+500ps which corresponds to 900ps when running at 5Gb/s (UI=200ps I assume).

    What happens when the DSP is connected to a standard PCIe chip interface (not another DSP) where the Tx-lane-to-lane is already equal to 1.3ns ( specified  in the PCI express base specification revision 2.0) ? The Rx budget is already exploded at the source.

    Should the Shannon only be connected to another Shannon ?

    THanks again.

    Bruno

  • 0 in reply to Bruno B
    TI__Mastermind 42545 points

    Hi Bruno,

    You are mixing our routing guidelines with the actual specification for the PCI express. You don't get to absorb all of the possible skew in the routing. If you look at the receiver specification table in the specification (table 4-12 in the version I have open), you will see that the allowable receiver skew is actually much larger then the 900ps we put in the routing requirements. In addition the PCIE Card Electromechanical spec defines the total interconnect skew as 1.6ns including 1.25ns on the system board and 350ps on the add-in card. After investigating this I'm going to recommend that the routing guidelines be changed from 2U+500ps to the 350ps allowed by add-in cards. We will add a note explaining that the normal PCIE connection is expected to be on the same PCB or to an edge connection to an add-in card. Either way the 350ps should be easily achieved. 

    Regards, Bill

  • 0 in reply to Bill Taboada
    Expert 1290 points

    Hi Bill,

    Thank you for your last investigations.

    I totally understand that there are some budget allocated for connectors, routings, Tx miss alignment and so. Therefore it is normal and necessary that the standard defines limits for each of them. But at the very end it is the receiver that must absorb the sum of all the individual skews.And as far as I can understand, this total amount of skew may be as large as 8ns (@ 5Gb/s)

    Therefore I think it is a minimum requirement that the DSP receiver circuitry tolerates a lane/lane skew of 8ns dictated by table 7-42

    Of course this brutal value can not be expressed in a routing guide without further explanations.But I would expect that in a simple case of part-to-part link within a same board, without any connector or so, the admissible skew at the DSP input be about 6 NS ( rx skew - tx_skew )

    I also agree that 350ps are easy to achieve but 5ns is even more easy : you simply have nothing to do.

    Please tell me if I am totally wrong.

    Afterwards I will close this post.

    With best regards,

    BRuno

  • 0 in reply to Bruno B
    TI__Mastermind 42545 points

    Hi Bruno,

    Are you wrong that a 6 ns skew would be within spec for the special case you proposed? No.

    However, you would be violating our routing guidelines. Since we are discussing the skew between two lanes of the PCI that are connecting two components, I can almost guarantee that having a difference of 6 ns (~34") of skew would require you to violate some of the other routing rules. We needed a guideline. The 900ps in the current KSII serdes implementation guidelines is generous, in my opinion overly generous, and easily achievable. We expect customers to follow those guidelines. High speed serdes routing requires care and providing a guideline that is too loose encourages designers to simply turn on the auto-router.

    Regards, Bill