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A9-CPU1 LED BLink Issue | OMAP4460

Dhiraj Vasudeva Shetty
Prodigy 20 points
Other Parts Discussed in Thread: 4460

Hello everybody,

#Test Setup

Ubuntu 12.04 x64 on Intel

OMAP 4460, Pandaboard ES Rev B1

Toolchain: arm-none-eabi- (Sourcery CodeBench Lite 2013.05-23)

U-Boot SPL 2011.12-rc1 (Sep 06 2013 - 15:42:53)

#Test Setup

We're just getting started with the A9 dual cores and our first exercise is to try to run two images of the same binary code on both of the A9 cores.

All code does is setup the respective PADCONF and blink the onboard LEDs D1 and D2:

  1. Binary 1: CPU0 blinks LED1 (GPIO_110).
  2. Binary 2: CPU1 blinks LED2 (GPIO_WK8).

So, the only difference between the two binaries is the GPIO that is controlled.

We also have Startup code that takes care of setting the entry points for CPU0 and CPU1 and for waking up CPU1.

The problem we face is that, the LED controlled by CPU1 always blinks at a much lower rate than that controlled by CPU0.

We have tried all possible combinations, switched the LEDs among the cores. The code attached tries to blink an LED on GPIO_137.

We still face the same issue, i.e. that the LED controlled by CPU1 always blinks much slower than the one controlled by CPU0.

We have tried to read the OMAP4460 TRM but we unable to find a setting that sets the CPU1 clock frequency.

Any pointers to help us look in the right direction is greatly appreciated. I have attached the code in this post.

Startup Script: 5734.startup.S

CPU0 Code: 0676.panda0.asm

CPU1 Code: 3513.panda1.asm

Thanks in advance for your help and support.

  • 0
    TI__Mastermind 29520 points

    Hello Dhiraj,

    I would suggest you to check your DPLL_MPU configuration. Refer to section 3.6.3.7 DPLL_MPU Descripton and Tactical Clocking Adjustment in OMAP4460 TRM.

    CM_MPU_MPU_CLKCTRL register manages the MPU clocks, and dividers described in section  Tactical Clocking Adjustment.

    Other information for MPU clock management can be obtained in section 4.3.6 Power Management, check the local MPU's PRCM registers.

    Registers which control CPU0 and CPU1 clock are CM_PDA_CPUi_CLKSTCTRL[1:0] CLKTRCTRL - 0x3: HW_AUTO: Automatic transition is enabled. Sleep and wake-up transition are based upon hardware conditions. Check this register to control the full domain transition of the CPU domain.

    Best regards,

    Yanko

  • 0 in reply to Yanko Todorov-XID
    Prodigy 20 points

    Hi Yanko,

    Thank you very much for your response. I really appreciate your help and support in helping us sort out this issue.

    Unfortunately, the power settings for each CPU (0 and 1) seem to point out that the error might be somewhere else.

    CPU1 is always in the ON (active) state, is not set up to go into sleep mode (NO_SLEEP mode is set).

    In spite of this, it seems funny that the same delay loop running on both cores leads to such a BIG difference - CPU0 toggles the LEDs in what seems to be micro-seconds. On the contrary, CPU1 takes around 2 seconds to toggle the LEDS. And CPU1 is running the exact same code.

    We have also tried using difference GPIO channels and also tried to run only CPU1. Even here the problem persists.

    From what I understand, both the cores are fed from the same clock, so that might not be the issue.

    Is there any other direction you could point us in, or do you think that we haven't been performing our tests (or writing our code) correctly?

  • 0 in reply to Dhiraj Vasudeva Shetty
    TI__Mastermind 29520 points

    Hello Dhiraj,

    I think that your issue with CPUs is caused from settings in the local clock generator in MPUSS. The picture below shows MPU clocks and switches for control.

    I suggest you to use Clock Tree Tool (CTT), which is available in TI web site - http://www.ti.com/litv/zip/swpc043

    In the attached file I tried to enable all clock signals to CORTEX A9. This file contains PRCM register addresses and values for settings. 4667.CORTEX_A9_Regs.txt

    Best regards,

    Yanko