How to access pcie registers beyond 0x1000?

Steve15

I have a c6657 pcie EP connected to a dm8148 pcie RC. I can successfully read and write to memory using BAR1..3 (mapped to L2, MSMC, and DDR). I'm using RBL with 6657 configured for PCIe boot (no IBL).

I'm trying to understand how to get access to pcie configuration registers beyond offset 0x1000 (such as MSI_CAP) so that I can configure the EP for MSI operations.

From the linux driver I'm using I get "Unhandled fault: Precise External Abort on non-linefetch ..." which I think is related to having BAR0 set up with a length of only 0x1000. Output from the code below is:

Bar[0] 0x2a000000, 0x1000

<< code snippet follows>>

    barStart [0] = pci_resource_start (ti81xx_pci_dev, 0);   /* BAR0 4K for PCIE application registers */
   barLen   [0] = pci_resource_len   (ti81xx_pci_dev, 0);
   barFlags [0] = pci_resource_flags (ti81xx_pci_dev, 0);
    printk(" Bar[%d] 0x%x, 0x%x\n", 0, barStart[0], barLen[0]);
    ...

    if (barFlags[0] & IORESOURCE_MEM) {
       regBase = barStart[0];
       /* Map the memory region. */
       request_mem_region(regBase, barLen[0], "DSPLINK");
   }
   else {
       /* Map the memory region. */
       request_region(regBase, barLen[0], "DSPLINK");
   }
   if (regBase > 0) {
       regVirt = ioremap(barStart[0], barLen[0]*4);
    }

over 13 years ago

0 lding over 13 years ago

TI__Guru* 95265 points

It seems that on RC side you are running a Linux program and EP side is the PCIE ROM bootloader. Since the EP side BAR0 size is hard coded, and after PCIE handshaking, the granted BAR0 lenght is 0x1000 bytes from RC side by checking with pci_resource_start(). Then from RC side with BAR0 you can only access the PCIE application register of EP.

With RBL, there are also BAR1/2/3/4 configured depending the switch pin setting, there BAR length are pretty big. Can you use BAR0 to change the IB translation register of EP side for one of the LL2/MSMC/DDR or the unused BAR4 to point to 0x2180_1000 for configuration registers? Will this work?

We have some example in C:\ti\mcsdk_2_01_02_06\tools\boot_loader\examples\pcie\linux_host_loader\pciedemo.c, e.g.void HAL_readDMA(uint32_t srcAddr, uint32_t dstAddr, uint32_t size, uint32_t flag),

iowrite32(EDMA_TPCC0_BASE_ADDRESS, pReg + IB_OFFSET(3)/4);

pReg = (uint32_t*)ddrVirt; /* Now it points to the start of EDMA_TPCC0_BASE_ADDRESS */

Where IB_OFFSET(3) was used for DDR originally, we temporarily changed it to point to EDMA_TPCC0. In your case, can you change this to 0x2180_1000?

I am not familiar with DM8148 PCIE memory space, if EP's configuration register is memory mapped into RC's (FOR 6657, it is 0x2180_2000 region), you write to this mapped region of RC side is equal to writing to the configuration register of the remote EP.

Regards, Eric

0 Steve15 over 13 years ago in reply to lding

Intellectual 385 points

I can't seem to access those PCIe registers. I tried first using BAR3/ddrVirt as you suggested, and when that failed tried BAR1/memVirt to see if anything was different. It seems that I can remap either BAR to point at the EDMA registers, but not to the PCIE configuration regs. Also, using 0x21800000, 0x21801000, 0x21802000, and 0x21803000 fail identically. All fail with the following output:

Read from l2 val =0xa930034
Remapped EDMA_TPCC0_BASE_ADDRESS+DMAQNUM0/4=0xa930034
L2 remapped (memVirt=0xd0000000)
Unhandled fault: Precise External Abort on non-linefetch (0x1028) at 0xd0000000
Internal error: : 1028 [#1]

and here is the code:

val = ioread32(memVirt+DMAQNUM0/4);
printk("Read from l2 val =0x%x\n",val);
iowrite32(EDMA_TPCC0_BASE_ADDRESS, regVirt + IB_OFFSET(1)/4);

val = ioread32(memVirt+DMAQNUM0/4);
printk("Remapped EDMA_TPCC0_BASE_ADDRESS+DMAQNUM0/4=0x%x\n", val);

iowrite32(0x21802000, memVirt + IB_OFFSET(1)/4);
printk("L2 remapped (memVirt=0x%x)\n", memVirt);
val = ioread32(memVirt+0);
printk("Read 0x%x from 0x2000\n", val);

0 lding over 13 years ago in reply to Steve15

TI__Guru* 95265 points

If that didn't work, can you access the RC's PCIe Remote Configuration Space (0x5100_2000 of DM8148), this is equivalent to access EP's configuration (0x2180_1000 of C6657)?

I looked at:

http://www.ti.com/lit/ds/sprs647d/sprs647d.pdf 8.17.1 PCIe Peripheral Register Descriptions

http://www.ti.com/lit/ug/sprugz8d/sprugz8d.pdf Figure 19-2. Address Space Zero Regions.

Regards, Eric

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How to access pcie registers beyond 0x1000?