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EDMA_LLD - C6670

aymeric dupont
Expert 1200 points


Dear support,

Up to now, I did not need more than 4 DMA channels to be allocated and following the answers from the following post, I got my four channels (http://e2e.ti.com/support/embedded/bios/f/355/t/242609.aspx) and I was happy,

Now I need more. I am confident that I know how to modify sample_c6670_cfg.c to make the adjustments that I want but I would like answers to a few questions that are confusing me. After reading (multiple time) section 1.1.1 of the user guide, I am quite confuse how this driver should be used across cores. I am confuse between the driver instance and the shadow register. Perhaps you could provide a bit more information.

On the C6670, I have 3 DMA controllers. See Table 7-33 EDMA3 Channel Controller Configuration of the reference guide.

Therefore the EDMA driver defines three instances of the driver. Each instance of the driver is configured following the hardware in sampleEdma3GblCfgParams

Then the resources for each driver are configured per shadow region. So if I take the specific case of the C6670, first instance.

for reg0: Ch0 and ch1 are reserved for hardware, then ch2 and ch3 for the sw

for reg1: Ch4 and ch5 are reserved for hardware, then ch6 and ch7 for the sw

for reg2: Ch8 and ch9 are reserved for hardware, then ch10 and ch11 for the sw

for reg3: Ch12 and ch13 are reserved for hardware, then ch14 and ch15 for the sw

And now my 16 channels are allocated.

In the concept of using the same driver library in all cores.

1) where is the memory of the driver being stored? Internal L2

2) How the C6670 use the EDMA driver?

    a) The manual seems to suggest for each master to use a different instance of the driver, however,. I have four cores and three instances of the driver?

   b) Should each core use a different shadow region of the same instance of the driver? driver

   c) I can do whatever I want as long as I undserstand what I am doing?

If answer C is the provided one, can you guarantee that there will not be conflict accessing the data structures stored in memory?

Thanks in advance for a bit of clarification

Aymeric

  • 0
    TI__Intellectual 1870 points

    Aymeric,

    The data of LLD are typically stored in L2 SRAM.

    All the instances can be used by all the cores.

    Shaddow Region should be used when multicores are involved.  The LLD driver implicitly takes care of the Shaddow Region when it allocates resources.  So you don't need to worry about Shaddow Region.  If CSL is used, you do need to explicitly configure the Shaddow Region.

    Xiaohui

  • 0 in reply to Xiaohui Li
    Expert 1200 points

    Thanks so much for this prompt answer. I got it now and digging a bit more in the driver using debugger helped a lot.

    I have one doubt about the configuration.

    I understand how I must allocate the Params, dma and QDMA in between regions. I know how many I have from the C6670 reference guide. I have many more params than I have channels to enable chaining which I also understand.

    What are the "ownTccs" . I found the following in the EDMA user guide:

    17-12 TCC 0-3Fh Transfer complete code. This 6-bit code sets the relevant bit in the chaining enable register (CER [TCC] /CERH
    [TCC]) for chaining or in the interrupt pending register (IPR [TCC] / IPRH [TCC]) for interrupts.

    I do not know how many I have and how they are used. Are they mapped one to one with the DMA channels?

    Thanks in advance

    Aymeric

  • 0 in reply to aymeric dupont
    TI__Intellectual 1870 points

    Aymeric,

    TCC field is used to specify a DMA channel you want to chain or the interrupt bit in IPR/IPRH you want to set once the DMA transfer is complete.

    For a DMA transfer of a particular DMA channel, if you want to chain this transfer to another DMA channel, then you need to put the DMA channel to be chained to in the TCC field of the PaRAM for the current DMA transfer.  On the other hand, if you want EDMA to generate an interrupt once a DMA transfer is complete, then you need to specify the TCC field to the bit in IPR/IPRH you want to set once the DMA transfer is complete.

    For example, assuming you want to do 2 DMA transfers by ch0 and ch1 and you wan tto chain ch0 to ch1.  Once the 2nd DMA transfer by cvh1 is complete, you want EDMA to generate an interrupt 8 in IRP.  Then you need to config TCC of PaRAM for ch0 to ch1 and put the number "8" in the TCC field of PaRAM for ch1.

    Xiaohui