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AM335X DDR2 PHY calibration

Peng Liu50174
Expert 1510 points

Other Parts Discussed in Thread: AM3359

Hi,

Is there any application note, guide or reference code  for AM335X processor DDR2 PHY calibration procedure? 

Peng

 

  • 0 in reply to Biser Gatchev-XID
    Expert 1510 points

    Hi, Biser,

    The calibration I mentioned is about setting the value of DDR2  PHY Registers such as DATAx_PHY_RD_DQS_SLAVE_RATIO,

    DATAx_PHY_FIFO_WE_SLAVE_RATIO,

    DATAx_PHY_WR_DQS_SLAVE_RATIO,

    DATAx_PHY_WR_DATA_SLAVE_RATIO

    CMDx_PHY_CTRL_SLAVE_RATIO.

    I tried using the Ratio Seed spreadsheet to calcuate these registers value, but some boards can't work with the calcuated value.

    Someone told me that in XLDR S/W  can try different value of these registers fields( such as scanning WR_DQS_SLAVE_RATIO_CS0 from 0 to 1023) to find one suitable register value windows, and then select the mean value. This method looks workable on our PCAs. Is this method a typical or normal way for PHY calibration?

    Regards,

    Peng.

     

     

  • 0 in reply to Peng Liu50174
    TI__Guru**** 393215 points
    Hi Peng,
     
    Are the boards that don't work properly exactly the same as those that work? Are the memory chips the same? I haven't heard of any iterative software for DDR2. There is a tuning process, but it's valid for DDR3 memories.
  • 0 in reply to Biser Gatchev-XID
    Expert 1510 points

    Hi, Biser,

    All the boards are same on PCB/PCA, same DDR2 chips.

    We first copied the setting from the AM3359 EVM, and most of boards were working well.

    However in our recent build, we built more boars, and found that 20% boards could not work well and were not stable. We re-calcuated the PHY register setting using the tool RatioSeed_AM335x_boards.xls. But these recalculated PHY setting didn't work either. Then our S/W engineers did iterative apporaching to get the suitable PHY registers value window, choosing the mean value, then now, the boards are working fine and stably.

    So we guess there might such one iterative method for DDR2.

    BTW: I found in our PCB DDR signal routing, some section of CK/DQS signals are running in the inner layers, while some section on the outer layer, therefore the 180ps/inch delay in that RatioSeed_AM335x_boards.xls is not fully suitable for us.So I should use the total delay in CK/DQS to re-calcuate the PHY register value, maybe this will come out with more appropriate estimated value.

    Regards.