This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

C66 Hello World and Endianess

I tried building the hello world program from the CCS, but after building it I get

C66xx_6: GEL: File: /home/fg716463/workspace/hello_world/Debug/hello_world.out Does not match the target endianness, not loaded. Check project build options and target configuration file (ccxml).

I tried switching "Device endianess" in Properties - General - Advanced Settings, but neither little nor big seem to be working.

As for the target configuration file I did not find where to set the endianess.

Can somebody point me out to what I am doing wrong?

  • You need to check the endianess in the Build Options for what you're building the .out file for.  And it needs to be what the endianess of what the board is set to.  At TI we tend to use Little Endian by default.

    Note if you're using a simulator, you need to select the simulator with the correct endianess.

    This isn't an option in Target Configurations, which has two potential items 1.) Simulator - In this case you select the simulator with the endianess you want.  2.) Emulation - In this case you set the board/device to be boot the device in the endian mode you need, for EVMs this information would be in your EVM documentation on how to do this.

    Best Regards,

    Chad

  • I assumed little endian, but as I tried it each, big and little endian and it failed with both of them (same error), I am a little confused.

    If little endian is wrong, shouldn't big endian then be correct as there is only these two options?

    I am using the TI XDS2xx USB Emulator for the XTCIEVMK2X EVM.

    The DIP is set to Uboot (0010)

     

  • You're correct it the board should be one endianess or the other, and you shouldn't get that error message if you tried .out files generated with little, rebuilt and generated with big endian.

    Just to confirm.  Did you set the endianess of the project, build the code and try to load.  Change the endianess to the opposite endian, rebuild and try to load the rebuilt code?  If you just change the endianess of the project and don't rebuild the code then it would still be a .out file of the original endianess, which we don't know what endianess it is unless we built it in the project knowing the build options.  

    I'd also suggest checking the timestamp when loading, to make sure you're not grabbing some older .out file that had been created.

    Best Regards,
    Chad 

  • Yes, I just double-checked it again, also the timestamp. The error occurs with both, little and big endian after a rebuild. 

    Best Regards,

    Frederick

  • One thing I find weird when looking at the error message is the GEL: File portion, are you attempting to load the code via a GEL file? 

    If you are trying to use a GEL file to load the code, please try to load it manually.

    Also, the following may help debug what's going on.

    Please look at Bit 8 of the CSR (Control Status Register) it should be in the list of Core Registers.  

    If this is 0, then it's Big Endian

    If this is 1, then it's Little Endian

    Please build a version that matches, the endianess of the board.  If this isn't working, then if you can send me the .out file so I can try it, that might be useful.

    Also, to be clear, can you provide a screen capture of the window when you have the core selected and are attempting to load the code.  

    Best Regards,
    Chad 

  • First i switched the endianess to big

    I then rebuilt the project

    I verified, the file is up to date

    I debugged the project: The error occured

    I then switched the endianess to little

    Rebuilt the project

    Verified, the file was up to date

    And got the same error again when debugging it.

    Also, this is the version of my CCS.

    What is a GEL file? I am new to developing with TI devices.

    Where or how would I figure out the CSR of the DSPs?

    Thanks for your help,

    Frederick Gnodtke

  • Can you please look at the details when loading the files?  I have a suspicion that you're unintentionally loading an old built .out file - Click Run -> Load -> Browse in the upper right of the browsing window you should be able to change the view to 'details' so you can see the date of the file you're loading (not what you're building which you've shown, but what you're loading.)

    The CSR should be in the register view.  Click CCS Debug so you're in Debug Mode, now click View->Registers a new window pops up, click Core Registers, scroll down to the CSR registers.

    Best Regards,

    Chad

  • When I open Run -> Load, everything is greyed out. However, after building I can see le/be in my Project view behind the executables. I assume, that stands for little endian/big endian, so the endianess definitly changes.

    The registers view is empty, even though the connection seems to work.

  • You say when you hit Run -> Load everything is greyed out.  That would mean you aren't even attempting to load something, at least not through the Debuger.   How were you attempting to load before, I'm guessing some sort of GEL script like I mentioned earlier.

    That said, it sounds like you haven't connected the Target (and possibly haven't setup and launched the target configuration.)  There should be documentation that came with the EVM that walks you through this.  If not, use the Help menu in CCS to install and launch a target configuration.