GPMC_ADVn_ALE is Low active, but it is driven to Low in a inactive cycle.
Sitara AM335x ARM Cortex-A8 Microprocessors (MPUs) (Rev. F)
http://www.ti.com/lit/ds/sprs717f/sprs717f.pdf
Figure 5-26. GPMC and Multiplexed NOR Flash - Asynchronous Read - Single Word
Figure 5-27. GPMC and Multiplexed NOR Flash - Asynchronous Write - Single Word
Can it be configured that the GPMC_ADVn_ALE is kept driven to High during a inactive cycle?
Best regards,
Daisuke
