SYSBIOS Cache API, XMC prefetch buffer, and C66 Silicon Errata

Dmitry Korenev

Other Parts Discussed in Thread: SYSBIOS

Could anyone explain to me why SYSBIOS implementation of Cache API for C66x distinguishs between global ("All") and block coherency operations?

Namely implementation of block coherency operations take into account XMC prefetch buffer (invalidate it as well, if necessary) and provide workaround for the notorious Advisory 22 (sprz334e.pdf) whereas implementation of global coherency opetations ignores XMC and, which is even more important, ignores the silicon bug altogether? I couldn't find any hint in the documentation...

SYSBIOS vestion: 6.33.06.50

Thanks in advance,

Dmitry

over 12 years ago

0 Steven Connell over 12 years ago

TI__Mastermind 45025 points

Hi Dmitry,

Which hardware platform are you working on?

Steve

0 Dmitry Korenev over 12 years ago in reply to Steven Connell

Intellectual 370 points

Hi Steve,

We use C6678 (EVM for now but we plan to design a custom board later)

Dmitry

0 judahvang over 12 years ago

TI__Mastermind 32475 points

Dmitry,

Originally, the L2 Cache corruption only affected the Block Coherence Operation (Advisory 7) so that is why we took measure to fix the Block Coherence APIs. With Advisory 22 affecting both block and global operations, I agree that we need to relook at the global operations. I believe the only global operation affected would be Cache_wbInvAll() as Cache_wbAll() is not affected and we don't support Cache_invAll().

As far as the XMC prefetch buffer, I think you are correct, this is an oversight. We should just invalidate the prefetch buffer regardless of whether any of the prefetch bit is enabled in the MAR registers.

We currently have an open issue, SDOCM00073425, to look at this.

Judah

0 Dmitry Korenev over 12 years ago in reply to judahvang

Intellectual 370 points

Judah,

Thank you for the explanation

Regards,

Dmitry

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SYSBIOS Cache API, XMC prefetch buffer, and C66 Silicon Errata