DM355 EMIF controller may not correct the 4 convert bit on one page, if we don't add some delays on calculation, following was what I found.
EMIF controller 4 bit ECC reads:
1. Set the (4BITECC_START) bit in the NAND Flash Control register (NANDFCR ) to 1.
2. Read 518 bytes of data from the NAND Flash.
3. Clear the (4BITECC_START) bit in the NAND Flash Control register (NANDFCR) by reading any of the NAND Flash 4-Bit ECC registers.
4. Read the parity stored in the spare location in the NAND Flash.
5. Convert the 8-bit parity values to 10-bits. Reverse of the conversion that was done during writes.
6. Write the parity values in the NAND Flash 4-bit ECC Load register (NAND4BITECCLOAD). Write each parity value one at a time starting from 4BITECCVAL1 to 4BITECCVAL8.
7. Perform a dummy read to the NAND Flash Status register (NANDFSR). This is only required to ensure time for syndrome calculation after writing the ECC values in step 6.
8. Read the syndrome from the NAND Flash 4-Bit ECC 1-4 registers (NAND4BITECC[4:1]). A syndrome value of 0 means no bit errors. If the syndrome is non-zero continue to step 9.
9. Set the (4BITECC_ADD_CALC_START) it in the NAND Flash Control register (NANDFCR) to 1.
10. Start another read from NAND if required (a new thread from step 1).
11. Wait for the 4-bit ECC correction state field (ECC_STATE) in the NAND Flash Status register (NANDFSR) to be equal to 0x1, 0x2, or 0x3.
12. The number of errors can be read from the 4-bit number of errors field (ECC_ERRNUM) in the NAND Flash Status register (NANDFSR).
13. Read the error address from the NAND Flash Error Address 1-2 registers (NANDERRADD[2:1]). Address for the errored word is equal to (total_words_read + 7 - address_value). For 518 bytes, the address will be equal to (525 - address_value).
14. Read the error value from the NAND Flash Error Value 1-2 registers (NANDERRVAL[2:1]). Errors can be corrected by XORing the errored word with the error value from the NAND Flash Error Value 1-2 registers (NANDERRVAL[2:1]).
I deliberately modify 4bit data at one page on kernel image, at step 11, we got NANDFSR ECC_STATE equal to 1, means too many errors to be correct. while I add some delays before step 10, we got NANDFSR ECC_STATE equal to calculation complete, and the error bit can be correct by hardware.
relate code :
nand_dm355_4bit_readecc(mtd, hw_4ecc);
if (hw_4ecc[0] == ECC_STATE_NO_ERR && hw_4ecc[1] == ECC_STATE_NO_ERR &&
hw_4ecc[2] == ECC_STATE_NO_ERR && hw_4ecc[3] == ECC_STATE_NO_ERR)
return 0;
val = *(dv_reg_p)NANDERRADD1;
emif_addr->NANDFCR |= (1 << 13);
do {
iserror = emif_addr->NANDFSR & 0xC00;
} while (iserror);
// we need to add some delay here, or else ecc state will be too many errors, any explanations on this?
/*
for(i=0,i<1;i++)
udelay(this->chip_delay);
*/
iserror = emif_addr->NANDFSR;
iserror &= EMIF_NANDFSR_ECC_STATE_MASK;
iserror = iserror >> 8;
if (iserror == ECC_STATE_NO_ERR)
return 0;
else if (iserror == ECC_STATE_TOO_MANY_ERRS)
{
printf("too many erros to be corrected!\n");
return -1;
}