MSP430 SYS/BIOS UCS Configuration

Hi Fred,

Ok, I've spoken with some folks and have a better understanding of what you need to do here.  Unfortunately you cannot *change* these clock settings via the SYS/BIOS configuration file, but you can disable those default settings (8192000 Hz, etc.) and then change them in C code. 

In addition to this, you must configure the BIOS cfg file to match the clock frequencies that you will set at run time.

Here's the overview of the steps you need to take:

1. Disable the default clock configuration/initialization
2. Tell BIOS the clock frequency values that you want to configure.  This tells BIOS "what to expect."
3. Configure the clocks to the frequencies that you want at run time (in main()).

Step 1. Allows you to override the default values that are being set for you.  The following config code will do this (add to your *.cfg file):

var Boot = xdc.useModule('ti.catalog.msp430.init.Boot');
Boot.configureDCO = false;

Step 2. This is also done in the *.cfg file and must be done so that BIOS "knows what you will do" at run time (it doesn't actually change the clock frequency).  In other words, you need to configure the ClockFreqs module with the frequency settings that will be made at run time.  You are already doing this in the config code that you posted:

ClockFreqs.SMCLK = 15000000;
ClockFreqs.ACLK = 32768;

Step 3. Is where you will actually configure the clock frequencies to have the values that you want.  In this step, you will call/add some C code that makes the actual changes to the registers to change the clock frequencies.

There are multiple ways you can implement step 3.

A) Copy and modify the boot code that runs by default, changing the frequencies as needed.

The following function is the default one that runs automatically.  This is what you *prevent* from running by performing step 1 above.  You can add this into your C file, update it as desired, then call it from main() before the call to BIOS_start():

/*
*  ======== Boot_configureDCO ========
*  Initializes MSP430F5xxx clocks and DCO for:
*      ACLK = REFO = 32768Hz
*      MCLK = SMCLK = 8.192MHz
*  Derived from the msp430x54x_UCS_3.c and MSP430F552x_UCS_03.c examples.
*/
#if defined(__ICC430__)
    #pragma location="CSTART"
#endif
Void Boot_configureDCO(Void)
{
    REG(UCSCTL3) |= SELREF_2;           /* set FLL ref to REF0 */
    REG(UCSCTL4) |= SELA_2;             /* set ACLK to REF0 */

    __bis_SR_register(SCG0);            /* disable FLL */
    REG(UCSCTL0) = 0x0000;              /* set lowest DCOx and MODx bits */
    REG(UCSCTL1) = DCORSEL_5;           /* select 24 MHz range */

    REG(UCSCTL2)  = FLLD_1 + 249;       /*
                                         * set multiplier for 8.192MHz:
                                         *     (N + 1) * FLLRef = Fdco
                                         *   (249 + 1) * 32768  = 8.192 MHz
                                         *      FLL Div = fDCOCLK/2
                                         */

    __bic_SR_register(SCG0);            /* enable FLL */

    /*
     * worst-case settling time (MCLK cylces)
     *    =  N x 32 x 32 x f_MCLK / f_FLL_ref
     *
     * 250000 =  32 x 32 x 8 MHz / 32768 Hz
     */
    __delay_cycles(250000);

    /* wait until XT1, XT2, and DCO fault flags are cleared... */
    do {
       REG(UCSCTL7) &= ~(XT2OFFG + XT1LFOFFG + XT1HFOFFG + DCOFFG);
       REG(SFRIFG1) &= ~OFIFG;
    } while (REG(SFRIFG1) &OFIFG);
}

B) Or you can use MSP430Ware APIs to configure the clocks.  This should be the one that you need. Note that there may be other APIs needed from MSP430Ware:

//*****************************************************************************
//
//! \brief Initalizes a clock signal
//!
//! This function initializes each of the clock signals. The user must ensure
//! that this function is called for each clock signal. If not, the default
//! state is assumed for the particular clock signal. Refer MSP430Ware
//! documentation for UCS module or Device Family User's Guide for details of
//! default clock signal states.
//!
//! \param baseAddress is the base address of the UCS module.
//! \param selectedClockSignal selected clock signal
//!        Valid values are:
//!        - \b UCS_ACLK
//!        - \b UCS_MCLK
//!        - \b UCS_SMCLK
//!        - \b UCS_FLLREF
//! \param clockSource is clock source for the selectedClockSignal
//!        Valid values are:
//!        - \b UCS_XT1CLK_SELECT
//!        - \b UCS_VLOCLK_SELECT
//!        - \b UCS_REFOCLK_SELECT
//!        - \b UCS_DCOCLK_SELECT
//!        - \b UCS_DCOCLKDIV_SELECT
//!        - \b UCS_XT2CLK_SELECT
//! \param clockSourceDivider selected the clock divider to calculate
//!        clocksignal from clock source.
//!        Valid values are:
//!        - \b UCS_CLOCK_DIVIDER_1 [Default]
//!        - \b UCS_CLOCK_DIVIDER_2
//!        - \b UCS_CLOCK_DIVIDER_4
//!        - \b UCS_CLOCK_DIVIDER_8
//!        - \b UCS_CLOCK_DIVIDER_12 - [Valid only for UCS_FLLREF]
//!        - \b UCS_CLOCK_DIVIDER_16
//!        - \b UCS_CLOCK_DIVIDER_32 - [Not valid for UCSFLLREF]
//!
//! Modified bits of \b UCSCTL5 register, bits of \b UCSCTL4 register and bits
//! of \b UCSCTL3 register.
//!
//! \return None
//
//*****************************************************************************
void UCS_clockSignalInit( uint32_t baseAddress,
                          uint8_t selectedClockSignal,
                          uint16_t clockSource,
                          uint16_t clockSourceDivider
                          )
{
        assert(
                (UCS_XT1CLK_SELECT == clockSource) ||
                (UCS_VLOCLK_SELECT == clockSource) ||
                (UCS_REFOCLK_SELECT == clockSource) ||
                (UCS_DCOCLK_SELECT == clockSource) ||
                (UCS_DCOCLKDIV_SELECT == clockSource) ||
                (UCS_XT2CLK_SELECT == clockSource)
                );

        assert(
                (UCS_CLOCK_DIVIDER_1 == clockSourceDivider) ||
                (UCS_CLOCK_DIVIDER_2 == clockSourceDivider) ||
                (UCS_CLOCK_DIVIDER_4 == clockSourceDivider) ||
                (UCS_CLOCK_DIVIDER_8 == clockSourceDivider) ||
                (UCS_CLOCK_DIVIDER_16 == clockSourceDivider) ||
                (UCS_CLOCK_DIVIDER_32 == clockSourceDivider)
                );

        switch (selectedClockSignal) {
        case UCS_ACLK:
                HWREG16(baseAddress + OFS_UCSCTL4) &= ~(SELA_7);
                clockSource = clockSource << 8;
                HWREG16(baseAddress + OFS_UCSCTL4) |= (clockSource);

                HWREG16(baseAddress + OFS_UCSCTL5) &= ~(DIVA_7);
                clockSourceDivider = clockSourceDivider << 8;
                HWREG16(baseAddress + OFS_UCSCTL5) |= clockSourceDivider;
                break;
        case UCS_SMCLK:
                HWREG16(baseAddress + OFS_UCSCTL4) &= ~(SELS_7);
                clockSource = clockSource << 4;
                HWREG16(baseAddress + OFS_UCSCTL4) |= (clockSource);

                HWREG16(baseAddress + OFS_UCSCTL5) &= ~(DIVS_7);
                clockSourceDivider = clockSourceDivider << 4;
                HWREG16(baseAddress + OFS_UCSCTL5) |= clockSourceDivider;
                break;
        case UCS_MCLK:
                HWREG16(baseAddress + OFS_UCSCTL4) &= ~(SELM_7);
                HWREG16(baseAddress + OFS_UCSCTL4) |= (clockSource);

                HWREG16(baseAddress + OFS_UCSCTL5) &= ~(DIVM_7);
                HWREG16(baseAddress + OFS_UCSCTL5) |= clockSourceDivider;
                break;
        case UCS_FLLREF:
                assert(clockSource <= SELA_5);
                HWREG8(baseAddress + OFS_UCSCTL3) &=  ~(SELREF_7);

                clockSource = clockSource << 4;
                HWREG8(baseAddress + OFS_UCSCTL3) |= (clockSource);

                HWREG8(baseAddress + OFS_UCSCTL3) &= ~(FLLREFDIV_7);
                //Note that dividers for FLLREF are slightly different
                //Hence handled differently from other CLK signals
                switch (clockSourceDivider) {
                case UCS_CLOCK_DIVIDER_12:
                        HWREG8(baseAddress + OFS_UCSCTL3) |= FLLREFDIV__12;
                        break;
                case UCS_CLOCK_DIVIDER_16:
                        HWREG8(baseAddress + OFS_UCSCTL3) |= FLLREFDIV__16;
                        break;
                default:
                        HWREG8(baseAddress + OFS_UCSCTL3) |= clockSourceDivider;
                        break;
                }

                break;
        }
}

Steve