This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

UART with EDMA3 in C6657

Hello, experts,

I use UART with EDMA3 in C6657, but it seems that the EDMA3 can't transmit data to UART.

When I use the EDMA3 to transmit data for memory to memory, it works good.

When I use UART whithout EDMA3, it works good.

But when I use UART with Edma3, it didn't work.

My code as below:


EdmaSend(5, srcBuffer, (void*)(0x2540000));//parameters: channel, source addr, dest addr(UART.THR)

int EdmaSend(uint32_t channelNum, void* srcAddr, void* dstAddr)
{
    ......//other code
    
    opt |= CSL_EDMA3_OPT_MAKE(CSL_EDMA3_ITCCH_EN,           \
                                  CSL_EDMA3_TCCH_DIS,       \
                                  CSL_EDMA3_ITCINT_DIS,     \
                                  CSL_EDMA3_TCINT_EN,       \
                                  channelNum,               \
                                  CSL_EDMA3_TCC_NORMAL,     \
                                  CSL_EDMA3_FIFOWIDTH_NONE, \
                                  CSL_EDMA3_STATIC_DIS,     \
                                  CSL_EDMA3_SYNC_AB,        \
                                  CSL_EDMA3_ADDRMODE_INCR,  \
                                  CSL_EDMA3_ADDRMODE_INCR );
    }
    myParamSetup.option  = opt;
    myParamSetup.srcAddr = (Uint32)srcAddr;
    myParamSetup.dstAddr = (Uint32)dstAddr;  //(Uint32)(&localUartRegs->THR)

    ......//other code

    CSL_edma3ParamSetup(hParam,&myParamSetup);
    
    ......//other code
}

  • I use EVM6657.

    Is the UART FIFO setting problem?

  • Any expert to help me?

    Please...

  • Jack,

    I am not sure if you set "DMAMOD1 = 1" in UART register which is a requirement for proper communication between the UART and the EDMA controller, as mentioned in UART user guide.

    Usually the user enables UART FIFO and UART interrupt support for DMA support that the specific EDMA channel will be triggered automatically based on UART TX/RX event.

    There are some threads discussing the UART/EDMA setup as well, such as follows:

    http://e2e.ti.com/support/dsp/c6000_multi-core_dsps/f/639/t/225788.aspx?pi267198=1

  • Steven,

    Thank you for your reply! I read the post you show me upon, and confim that I set "DMAMOD1 = 1" in UART register.

    My project is below, please have a look.

    5482.UART_EDMA.rar

    Thank you very much,

    Jack

  • Steven,

    I got it!

    The manual says only TC0 and TC2 can use for UART, But I use TC3 before!

    change to TC2, the program works good!

    Thank you!

    Jack

  • Hi Steven, Jack,

    I have been trying Jack's code (I hope you dont mind :)) because I am working with EDMA and UART transfers

    I have a question, more related to the EDMA transfer. If I place the buffers on the DDR I only see ony byte transfered into the DDR3 (37, which is weird). If I placed at least one of the buffers in L2SRAM I dont see any byte transfer at all. Do you have any idea what is it happening?

    Thanks in advance

    JaviEr

  • Javier,

    If you move buffer to L2SRAM, please make sure you are using global address as the source/destination address in EDMA OPT setup for L2, otherwise the transfer could not happen correctly.

  • Thanks Steven

    I had changed as well the ACNT BCNT (0x100,0x1) and now it transfers more data than 1 byte

    Javier

  • Hi again Steven,

    I think I have fixed it but still I am facing some problems with the UART transmission.

    So far I managed to transfer data through EDMA (by using global addresses instead local addresses and playing with ACNT and BCNT), and I managed to transfer data thorugh the UART.

    The problem comes when I want to transfer data through UART previously sent via EDMA. I checked the EDMA TC I am using is TC2 and also that DMAMODE1 bis is set to 1.

    Do I need to set as well the interrupt source in ETBEI bit?

    Thanks in advance

    JaviEr

  • Javier,

    If I understand your question correctly, are you trying to use UART DMA events ("URXEVT" and "UTXEVT") to trigger EDMA/UART transfer automatically please?

    ETBEI bit controls the UART CPU event "THREINT", not the DMA events. 

    If you want to offload CPU and use EDMA only for the transfer, you could use the specific EDMA channels triggered by UART events and do not need to set ETBEI bit.

    Please refer to section 2.9 DMA Event Support in UART user guide.

  • Hi Steven,

    I managed to get data out of the UART through the UART but I see now that there is a limitation in the data transferred.

    If I configure ACNT to 1 and BCNT to 16 I see 16 bytes coming out through the UART. If I configure ACNT to 1 and BCNT to 32, I still see only 16 bytes coming out through the UART. From this behaviour I guess there is a limitation in the input buffer of the UART (even if the BCNT can be configured up to the 65535). Is this related to the UART FIFO?

    I did another test and try to do two consecutive EDMA tranfers. If I dont set a breakpoint in between two transfers I only see the first. What I did to solve this is polling LSR->THRE bit until is 1 (what is related to the FIFO behaviour).

    My question is if there is any way of checking this without polling this bit in the edma isr.

    Thanks in advance

    JaviEr

  • Javier,

    The UART has 16-byte FIFO in both TX/RX. Once you enable FIFO and DMA event, EDMA channel should be triggered every time the TX FIFO is empty. You can try to setup ACNT=1, BCNT=FIFO_size (16), CCNT = Buff_size/FIFO_size (Buff_size more than 16 bytes) in  your EDMA setup.

    And in the EDMA ISR, you could also reset the UART module and enable it again later to match your synchronization requirement. Please take a look at the example in the following thread:

    http://e2e.ti.com/support/dsp/c6000_multi-core_dsps/f/639/t/290279.aspx

  • Hi Steven,

    I am using EDMA3 with UART transmit and receive on C6657. We have about one receive error in about 50MBytes transferred. But if we have transfer on another UART(B) port. There is no receive error. It seems that UART transmit causes error on receive on the same UART port.
    Does TI have C6657 silicon errata on this?
    Thank you.

    Steve Qu