Hi,
I am writing an application that does some image processing. My flow is:
- MVL program on ARM loads image data and writes it to shared memory area
- program on ARM starts off DSP code which does the hard work
- the DSP code writes the results back to a shared memory area
- the ARM writes the contents out to an NFS share for insepection
All of this seems to be working OK, until I come to turn on caching of the area that I am using for my heap. The memory map I am using is shown below (sorry for formatting, is there a better way?):
name origin length used unused attr fill
---------------------- -------- --------- -------- -------- ---- --------
IRAM 11800000 00020000 00020000 00000000 RWIX
CACHE_L2 11820000 00020000 00000000 00020000 RWIX
CACHE_L1P 11e00000 00008000 00000000 00008000 RWIX
L1DSRAM 11f00000 00006000 00006000 00000000 RWIX
CACHE_L1D 11f06000 00002000 00000000 00002000 RWIX
L3_CBA_RAM 80000000 00020000 00000000 00020000 RWIX
WARP_IN_MEM c2000000 0012c000 00000000 0012c000 RWIX
WARP_OUT_MEM c212c000 0012c000 00000000 0012c000 RWIX
WARP_WORKING_MEM c2258000 01800000 01800000 00000000 RWIX
RESET_VECTOR c3a58000 00000080 00000000 00000080 RWIX
SDRAM c3a58080 00400000 0005de84 003a217c RWIX
the program gets the speedup I'd expect, but many of the buffers seems to have their contents corrupted.
I have recompiled DSPLINK to incorporate the changes to the default memory map that have been made. My TCF file is included below.
Any suggestions would be greatly appreciated.
Greg
var mem_ext = [];
mem_ext[0] = {
comment: "4Mbytes of the DSP's DDR2 off-chip memory",
name: "SDRAM",
base: 0xC3A58080,
len: 0x00400000,
space: "code/data"
};
/* Specify the L1 and L2 memory settings */
var device_regs = {
l1PMode: "32k",
l1DMode: "8k",
l2Mode: "128k"
};
params = {
clockRate: 300,
catalogName: "ti.catalog.c6000",
deviceName: "L137",
regs: device_regs,
mem: mem_ext
};
utils.loadPlatform("ti.platforms.generic", params);
bios.enableRealTimeAnalysis(prog);
bios.enableMemoryHeaps(prog);
bios.enableTskManager(prog);
bios.IRAM.createHeap = true;
bios.IRAM.enableHeapLabel = true;
bios.IRAM["heapLabel"] = prog.extern("EXTMEMHEAP");
bios.IRAM.heapSize = 0x20000; // 128kb
bios.L1DSRAM.createHeap = true;
bios.L1DSRAM.enableHeapLabel = true;
bios.L1DSRAM["heapLabel"] = prog.extern("L1DHEAP");
bios.L1DSRAM.heapSize = 0x6000; // 24kb
bios.disableRealTimeAnalysis(prog);
bios.enableMemoryHeaps(prog);
bios.disableRtdx(prog);
bios.enableTskManager(prog);
prog.module("GBL").ENABLEALLTRC = false ;
prog.module("GBL").PROCID = parseInt (arguments [0]) ;
prog.module("GBL").C64PLUSCONFIGURE = true ;
prog.module("GBL").C64PLUSL1PCFG = "32k" ;
prog.module("GBL").C64PLUSL1DCFG = "8k" ;
prog.module("GBL").C64PLUSL2CFG = "128k" ;
// Enable MAR195 to cache range 0xC30000000 to 0xC3FFFFFF which
// is where the program data sits.
prog.module("GBL").C64PLUSMAR192to223 = 0x00000008 ;
// We would like to cache the range 0xC20000000 to 0xC2FFFFFF, but this appears
// to cause problems whereby the contents of this range and corrupted.
//prog.module("GBL").C64PLUSMAR192to223 = 0x0000000C ;
var WARP_IN_MEM = prog.module("MEM").create("WARP_IN_MEM");
WARP_IN_MEM.base = 0xC2000000 ;
WARP_IN_MEM.len = 0x12C000;
WARP_IN_MEM.createHeap = false;
WARP_IN_MEM.comment = "WARP_IN_MEM";
var WARP_OUT_MEM = prog.module("MEM").create("WARP_OUT_MEM");
WARP_OUT_MEM.base = WARP_IN_MEM.base + WARP_IN_MEM.len;
WARP_OUT_MEM.len = 0x12C000;
WARP_OUT_MEM.createHeap = false;
WARP_OUT_MEM.comment = "WARP_OUT_MEM";
var WARP_WORKING_MEM = prog.module("MEM").create("WARP_WORKING_MEM");
WARP_WORKING_MEM.base = WARP_OUT_MEM.base + WARP_OUT_MEM.len;
WARP_WORKING_MEM.len = 0x01800000;
WARP_WORKING_MEM.createHeap = true;
WARP_WORKING_MEM.heapSize = WARP_WORKING_MEM.len;
WARP_WORKING_MEM.comment = "WARP_WORKING_MEM";
var RESET_VECTOR = prog.module("MEM").create("RESET_VECTOR");
RESET_VECTOR.base = WARP_WORKING_MEM.base + WARP_WORKING_MEM.len;
RESET_VECTOR.len = 0x00000080;
RESET_VECTOR.space = "code/data";
RESET_VECTOR.createHeap = false;
RESET_VECTOR.comment = "RESET_VECTOR";
var SDRAM = prog.module("MEM").instance("SDRAM");
SDRAM.base = RESET_VECTOR.base + RESET_VECTOR.len;
SDRAM.len = 0x00400000;
SDRAM.space = "code/data";
SDRAM.createHeap = true;
SDRAM.heapSize = 0x10000;
SDRAM.comment = "SDRAM";
prog.module("MEM").ARGSSIZE = 50 ;
bios.MSGQ.ENABLEMSGQ = true;
bios.POOL.ENABLEPOOL = true;
bios.setMemCodeSections (prog, SDRAM) ;
bios.setMemDataNoHeapSections (prog, SDRAM) ;
bios.setMemDataHeapSections (prog, SDRAM) ;
prog.module("MEM").BIOSSEG = SDRAM;
prog.module("MEM").SYSINITSEG = SDRAM;
prog.module("MEM").TEXTSEG = SDRAM;
prog.module("MEM").BIOSOBJSEG = SDRAM ;
prog.module("MEM").MALLOCSEG = SDRAM ;
prog.module("TSK").STACKSEG = SDRAM ;
prog.module("MEM").STACKSIZE = 0x20000 ;
if (config.hasReportedError == false)
{
prog.gen();
}
