AM1808 UART interrupt by Receiver data-ready

Hi RY,

Thanks for your post.

I think, in your case, the Receive data-ready interrupt would have cleared where Rx. FIFO drops below the trigger level under any of the below cases and because of this, you are not able to assert the second interrupt.

1. if any new character received in the Rx FIFO?

2. The CPU or the EDMA controlller would have read atleast one character from the receiver FIRO with in the receiver time-out period which is more than four continuous character times and this triggers the receiver time-out interrupt. This shows that, it would have accessed the Rx. FIFO during the Rx. time-out period of four character times

The above would be the possible reason which the second Rx. data ready interrupt is not asserted.

Please make sure that you are not getting any receiver time-out interrupt or any receiver line-status interrupt which will be triggered based out of over-run error, parity error, framing error or a break if any, because line-status interrupt has higher priority than the receiver data-ready interrupt.

Also, Please validate your character times manually which shall be calculated by using the baud-rate and A character time is basically the time allotted for 1 START bit, n data bits, 1 PARITY bit and 1 STOP bit where n depends on the word length. Kindly make sure and examine that, you are not able to assert the second Rx. data interrupt more than the four character times (Rx. time-out period).

To address your second question, you are correct that, it is kind of Receiver data-ready interrupt which needs to be asserted and the INTID should be 010b.

Thanks & regards,
Sivaraj K

Sivaraj K-san,

Thank you so much for your advice.
I have not been able to understand enough how second interrupt is occured.
May I have additional question?

Is my following understanding correct?
1. UART receives data more than trigger level.
2. After a while, 1st receiver data-ready interrupt is occured.
3. After I read more than 1byte,
   when there are more than trigger level data in the RX FIFO,
   2nd receiver data-ready interrupt will occur.
Correct?

My use case of now (2nd interrupt does not occur)
1. UART receives data more than trigger level.
2. After a while, 1st receiver data-ready interrupt is occured.
3. After that, receiver data-ready interrupt is not occured.
4. Even after uart receives additional data, receiver data-ready interrupt is not occured.

Best regards, RY

Hi RY,

Thanks for your update.

I think, you understood in a different context. I apologise for your misunderstanding.

In general, if trigger level is reached, the UART FIFO will not accept any new data and what i mean to say here is, once the trigger level is reached, it will wait for the time duration of four character times as mentioned in Table 31-4 and of this duration, if you didn't find any access to UART FIFO, I mean, if the UART FIFO didn't drop below the trigger level which maintains the same trigger level as before, then the 2nd receiver data-ready interrupt will be asserted again.

Hope, you understood the above context.

Thanks & regards,

Sivaraj K

Sivaraj K-san,
Thank you so much for your helpful description.

Sivaraj Kuppuraj said:

if you didn't find any access to UART FIFO, I mean, if the UART FIFO didn't drop below the trigger level which maintains the same trigger level as before, then the 2nd receiver data-ready interrupt will be asserted again.

I think it is the same as my use case.
But, I have not been able to detect the 2nd receiver data-ready interrupt.

 - How should I fix my use case in order to detect the 2nd receiver data-ready interrupt?

Best regards, RY

Sivaraj K-san,
Thank you so much for your support.
If you need time to answer, I would like to ask as I get the time to customers.
Could you let me know the time you need?
Best regards, RY

Hi RY,

Kindly check the following:

1. Please validate your character times manually which shall be calculated by using the baud-rate and A character time is basically the time allotted for 1 START bit, n data bits, 1 PARITY bit and 1 STOP bit where n depends on the word length.

2. Please check any new character received in the Rx FIFO or whether it triggers any receiver time-out interrupt?