TI has recommended that I try to use DSPLink instead of Codec Engine. I've already converted the DSP code to be CE-free, I've created a "stub" ARM9 app that load the software via the PROC component. I'm now trying to implement a very primitive interface between the two processor halves via POOLs and NOTIFY.
I'm trying to abstract the instructions in DSP/BIOS LINK Programmer's Guide paragraph 4.2.5.2 to my application.
I am defining 16 pools of 3 different sizes. I searched my project looking for "POOL_config" and got a few hits:
Searching for 'POOL_config'...
In file C:\CCStudio_v3.3\bios_5_33_03\packages\ti\bios\include\pool.h62 ...
Line 36: ;# ======== POOL_config ========
Line 47: .asg "", POOL_config$regs
Line 48: POOL_config .macro _usePOOL
In file C:\CCStudio_v3.3\MyProjects\SPI test\SPI_TESTcfg.s62 ...
Line 381: ;; ======== POOL_config ========
Line 383: POOL_config _USEPOOL
5 occurrence(s) have been found.
I did not find a method of configuring this in DSP/BIOS Config. Can someone point me to the method of configuring this in CCS?
Also, my intent for this exercise is to put some "shared memory" in far memory. That is, I would like data that is parked in certain memory locations to be shared between the two processor halves. (The data in question is huge and definitely will not fit in the internal shared memory.) I understand that the GPP code must protect against accessing cached data. Other than that, can anyone explain whether this is impossible? (I'm willing to deal with difficult.)
