Having a problem in an OMAP5912 design with DSP DMA from McBSP1 to DSP internal DARAM memory. The DMA is supposed to run continuously after it is started, but sometimes it just stops. This seems to be related to activities on the ARM side in ways that are not clear. (See earlier post by Dennis Ochs describing an interaction with an ARM side CRC algorithm running on the flash memory on the slow bus.) We are now looking at the TIPB Control Mode Register (CMR).
I have already found that I must set the CPU_PRIORITY bit in this register to the non-default value of 0, thereby switching from a fixed priority scheme with the DSP DMA last, to a rotating priority scheme between DSP core, MPUI, and DSP DMA, in order to get this same DMA process to work reliably in the face of a timeout write to the Mailbox peripheral when it is already full.
I'm wondering about the other settings in this register. There are settings for timeouts and access-factors in two sets. I'm wondering about changes to the access-factor settings, but I would like a better understanding of what they do. These are at defaults, value 1, meaning accesses take 3 DSP-core clock cycles.
I'm wondering if it makes sense to try different values. Can I operate with access-factor = 0, moving down to 2 DSP-core clock cycles.
The timeout registers are at there default maximum values. Not sure if it might make sense to try reducing these.
If anyone has any wisdom to impart, it sure would be appreciated.
Thanks,
Joe Diederichs
Philips Healthcare