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DM3730 McBSP1 in DLB mode

Sujan Nag1
Prodigy 190 points
Other Parts Discussed in Thread: SYSCONFIG

Hello all,

I am working on devkit8500 board from Embest. kernel version 2.6.32.

I am trying to perform a simple Digital Loopback test to check McBSP1 interface.

I was able to build a simple driver, and load it successfully. The transmitter part is working, but due to some reason the RRDY bit in SPCR1 reg is always 0, and hence I am unable to get anything on the receiver section.

Here are the configuration settings I used:

struct omap_mcbsp_reg_cfg *config;

config = (struct omap_mcbsp_reg_cfg *)kmalloc(sizeof(struct omap_mcbsp_reg_cfg), GFP_KERNEL);

/*Digital Loopback*/
config->xccr |= (DILB);
config->xcr2 |= (XPHASE);
config->rcr2 |= (RPHASE);

 - all the other bits are in there reset state.

I went through section 21.4.2.4.3 of the TRM Rev. R, and decided to go with the reset values.

1. What are the appropriate settings required for operating McBSP in DLB mode?

Please guide.

Regards

Sujan

  • 0
    TI__Guru 65405 points

    Hi Sujan,

    Could you dump the value of all McBSP registers or at least dump the following registers:

    MCBSPLP_XCCR_REG
    MCBSPLP_SPCR2_REG
    MCBSPLP_SPCR1_REG
    MCBSPLP_RCR2_REG
    MCBSPLP_RCR1_REG
    MCBSPLP_XCR2_REG
    MCBSPLP_XCR1_REG
    MCBSPLP_SRGR2_REG
    MCBSPLP_SRGR1_REG
    MCBSPLP_PCR_REG
    MCBSPLP_SYSCONFIG_REG
    MCBSPLP_WAKEUPEN_REG
    MCBSPLP_RCCR_REG

    Check the schematic whether the receive signals are connected internally through multiplexers to the corresponding transmit signals:

    • DR signal is connected on DX signal to receive the transmitted data
    • FSR is connected to FRX output signal
    • CLKR is connected to the CLKX output signal

    Check the pinmux for pins related to McBSP.

    BR

    Tsvetolin Shulev

  • 0 in reply to Cvetolin Shulev-XID
    Prodigy 190 points

    Hello Tsvetolin,

    Thanks for the reply.

    Well, I did do the pin Muxing in u-boot. Well I am new to such development, so please have a look at the muxing values.

    Pin Mux Values:

    MUX_VAL(CP(MCBSP1_CLKR), (IEN | PTD | DIS | M0))
    MUX_VAL(CP(MCBSP1_FSR), (IEN | PTD | DIS | M0))
    MUX_VAL(CP(MCBSP1_DX), (IDIS | PTD | DIS | M0))
    MUX_VAL(CP(MCBSP1_DR), (IEN | PTD | DIS | M0))
    MUX_VAL(CP(MCBSP_CLKS), (IEN | PTD | DIS | M0))
    MUX_VAL(CP(MCBSP1_FSX), (IEN | PTD | DIS | M0))
    MUX_VAL(CP(MCBSP1_CLKX), (IEN | PTD | DIS | M0))

    I wanted to ask though, since I am working in DLB mode, does the directions for clock and frame sync matter?

    Also here are the register dump values, please have a look:

    omap-mcbsp omap-mcbsp.1: **** McBSP1 regs ****
    omap-mcbsp omap-mcbsp.1: DRR2: 0x0000
    omap-mcbsp omap-mcbsp.1: DRR1: 0x0000
    omap-mcbsp omap-mcbsp.1: DXR2: 0x0000
    omap-mcbsp omap-mcbsp.1: DXR1: 0x0000
    omap-mcbsp omap-mcbsp.1: SPCR2: 0x00c3
    omap-mcbsp omap-mcbsp.1: SPCR1: 0x0003
    omap-mcbsp omap-mcbsp.1: RCR2: 0x8000
    omap-mcbsp omap-mcbsp.1: RCR1: 0x0000
    omap-mcbsp omap-mcbsp.1: XCR2: 0x8000
    omap-mcbsp omap-mcbsp.1: XCR1: 0x0000
    omap-mcbsp omap-mcbsp.1: SRGR2: 0x1000
    omap-mcbsp omap-mcbsp.1: SRGR1: 0x0000
    omap-mcbsp omap-mcbsp.1: PCR0: 0x0c00
    omap-mcbsp omap-mcbsp.1: XCCR: 0x0020
    omap-mcbsp omap-mcbsp.1: RCCR: 0x0000
    omap-mcbsp omap-mcbsp.1: SYSCON: 0x0214
    omap-mcbsp omap-mcbsp.1: WAKEUPEN: 0x0408
    omap-mcbsp omap-mcbsp.1: DRR: 0x0000
    omap-mcbsp omap-mcbsp.1: ***********************

    Regards

    Sujan

  • 0 in reply to Sujan Nag1
    Prodigy 190 points

    Hello Tsvetolin,


    I was able to solve the previous issue, now I am able to read the DRR register, but its always 0. I am not able to receive anything.

    The altered register values are:

    omap-mcbsp omap-mcbsp.1: SPCR1: 0x0007
    omap-mcbsp omap-mcbsp.1: SRGR2: 0x101f

    I have FPER = 32, FWID = 1.

    Any suggestions?

    Regards

    Sujan


  • 0 in reply to Sujan Nag1
    TI__Guru 65405 points

    Hi Sujan,

    The pinmux configuration seems correct. The MCBSPLP_XCCR_REG[5] DLB bit is set therefore the Digital loopback mode is enabled but I find that the RRDY bit of MCBSPLP_SPCR1_REG[1] register is 1 which means that Receiver is ready with data to be read from DRR. I don't know the mechanism of your receiver but at this moment you should try to read the input data.

    BR

    Tsvetolin Shulev

  • 0 in reply to Cvetolin Shulev-XID
    TI__Guru 65405 points

    Sujan,

    Probably you have a problem with the clocking. You should enable CLKXM bit of the MCBSPLP_PCR_REG register. Try to set the MCBSPLP_PCR_REG to 0x0e00. The FSRM and FSXM bits should be set but you did this yet. This could be seen at Figure 21-26 Conceptual Block Diagram for Clock and Frame Generation.

    Also look at the Table 21-19 for your case - DLB=1 ALB = 0 (Digital loop back mode enabled and Analog loop back mode disabled) whether all effects are implemented.

    BR

    Tsvetolin Shulev

  • 0 in reply to Cvetolin Shulev-XID
    Prodigy 190 points

    Hello Tsvetolin,

    Thanks for the inputs. Well I did the alteration as per CLKXM and CLKRM is concerned, and also checked for Table 21-19. All seems to be in place. 

    Also I selected McBSP1_ICLK as the clock to SRG. Nothing changed.

    I am attaching my simple driver file along with this post. Well I changed my code to single phase for simplicity. Please have a look, on what I am missing.

    Regards

    Sujan

    3644.mcbsp_DLB.c