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PLL1 settings going wrong

gorge ss
Prodigy 160 points

Hi 

Im using Omap L138 and am adjusting the speed of the peripherals, i have some questions regarding the PLL1 clocks. Currently my setting for PLL1 are as follows (OSCIN : 24Mhz).

I would want the spi1 clk to be > 50Mhz, but am unable to acheive this, could anyone plz check what am i doing wrong.

i understand the SPI1 is driven by PLL1_sysclk2 which is 150Mhz in my case. so i should obtain 75Mhz as input to spi.

PLLREF : 24
PLLM : 25
This makes Async2_domain clk : 150Mhz

Async3_CLKSRC : PLL1_sysclk2

Postdiv : 2
PLLDIV1 : 1
PLLDIV2 : 2 --> sysclk2 : 150Mhz
PLLDIV3 : 3

  • 0
    TI__Expert 4760 points

    Hi Gorge,

    By default the SPI1 uses PLL0_SYSCLK2, but these modules can be configured as a group to use PLL1_SYSCLK2 by programming the ASYNC3_CLKSRC bit in the chip configuration 3 register (CFGCHIP3) of the system configuration (SYSCFG) module

     Please refer the TRM SPRUH77A page no 150 for more details

    And also according to your settings

    PLLREF = 24 MHz

    PLLM =25

    POSTDIV=2

    PLLDIV1=1

    PLLDIV2=2

    PLLDIV3=3

    You’ll be getting PLL1_SYSCLK2 =69.333 MHz

    The maximum supported frequency for PLL1_SYSCLK2 is 152MHz, if we operated it under 1.3 Volt, Please refer the datasheet SPRS586F page no 94 for more details.

    Also refer the advanced PLL calculator spreadsheet for peripheral clocking usage

    http://processors.wiki.ti.com/index.php/File:SYS_CLK_CALC_OMAP-L138_C674X_AM18X_v1p0.zip

     

    Regards

    Antony

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