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PLL configuration discrepancy

Slobodan Gataric
Expert 1020 points

I found conflicting information in the C6678 Data Manual (SPRS691D.pdf). It is regarding the PLL configuration.

Page 41 gives an equation for the output clock:

CLK = CLKIN x ((PLLM+1) / (OUTPUT_DIVIDE x (PLLD+1)))

I understand that default reset values for PLLM and PLLD are "0" so that these do not change the output clock frequency by the default. However, there is a problem with OUTPUT_DIVIDE. Page 143, figure 7-8 says that the default reset value of OUTPUT DIVIDE is "1". Table7-15, on the same page, says:

Bit 22-19 , OUTPUT DIVIDE, 1h = /2. Divide frequency by 2.

This does not match the equation from page 41. If the default value of OUTPUT_DIVIDE is 1, according to the equation there is no frequency change since the total multipler is "1".

Should the equation from page 41 be:

CLK = CLKIN x ((PLLM+1) / ((OUTPUT_DIVIDE+1) x (PLLD+1))) ?

Bottom line question is: Does the input frequency get through unchanged or it is divided by two after the reset?

Thank you.

Gasha

 

 

  • 0
    TI__Mastermind 30825 points

    After reset (before booting) the device is in Bypass.  After Boot ROM execution (except I2C, SPI and No-boot) it uses the Devspeed of the device and indicated input clock speed to program the PLL based on the values in Table 2-24 (pg 41.)  That said the device defaults to OUTPUT_DIVIDE of 1h (or Divide by 2.)  Note that when it bypass this is bypassed.

    Page 41 looks like it needs updated.  The bit field OUTPUT_DIVIDE of 2h is not valid (it would be a reserved value.) It looks like it was meant to indicate that that's a divide by 2 by default (after boot and the device BootROM has configured the PLL.)

    I'll let the document owner know of the issue so it can be corrected.

    Best Regards,

    Chad

  • 0 in reply to Chad Courtney
    Expert 1020 points

    I am still mising the big picture here. Are you saying that in the case of SPI boot (Boot mode [12..10] =  0b110), the PLL stays in bypass mode? What is the purpose of raw 7 in Table 2-24? My understanding is that raw 7 shows how PLL is initilized when boot mode is 0b110 (from Table 2-5,  0b110 = 6 = SPI). If SPI boot makes PLL stay in bypass then this raw should not be shown, or it should say "Stays in bypass". Could you explain this please? Also, are the shown input clok frequencies in Table 2-24, the frequencies I have to use for each boot mode or I can go slower?

    One more thing that  is very important to get 6678 SPI boot propely. What clock is used to clock the boot data out of SPI flash? I checked for the definitions of where SYSCLK1 to SYSCLK11 are used for, but I did not find that any was used as SPI Clock. So, here is very concrete question: If I have 100MHz clock coming in and I select SPI boot, what will be the default SPI clock coming out during the SPI boot? That is essential piece of information in order not to overclock boot SPI flash. However, that is almost impossible to find in the documentation. I am very interested if you could point out where is that information in the portfolio. It is certanly not in the booting guide where I would expect to find anything I need to know about the dsp booting. SPI boot loader chapter is a third of a page and it does not contain any hardware information (like the question i just asked).

    Thank you.

    Gasha

     

  • 0 in reply to Slobodan Gataric
    TI__Mastermind 30825 points

    Yes, for SPI it stays in Bypass unless you provide the info to set the PLL's in the SPI boot code.  I believe there's a header to do that (so that you don't have to program the registers per se but the Boot ROM takes care of that.)  I'll add on one of our Boot Experts to explain this.  Also see the SPI boot configuration section 2.5.2.6 and you'll see those pins are used for something else.  I believe this is also explained in the Bootloader's UG.

    Section 7.5.5 gives the PLL timings.  25ns max cycle time, so it can go down as low as 40MHz input clock. And then you'd program the PLL to bring it out of bypass.  If you're using one of the bootmodes that automatically set the PLL based on the table settings, I'd suggest using the next frequence above the one your input clock frequency is, to be as close to but below the max operating frequency when it initially sets the PLL.  Then reprogram the PLL in your boot code.

    SPI is clocked off of SYSCLK7 which is CPU/6 

  • 0 in reply to Chad Courtney
    Expert 1020 points

    So, although you did not say it, it looks like the Table 2-24 in 6678 Manual gives wrong information. "0b110" raw should say "PLL stays in bypass mode so the input clock is not changed regardless of the speed grade". That is one more thing to fix in the documentation.

    We are using 100Mhz clock source se we should be fine. Thank you for the information. My concern was what happens before user application is running because I could not understand and find default values and operating conditions. The SPI flash we use can run at 54MHz max. It is essential not to overclock it, otherwise the dsp will not boot. In the case that 100MHz clock was the SPI clock, it would not work.

    I am still curious, what pdf file has the information that SPI clock uses SYSCLK7? I searched SPI user guide (SPRUGP2A) for "SYSCLK7" and got that no matches were found. Then I searched entire portfolio and found SYSCLK7 only in the dsp user manuals (6670, 6671, 6672, 6674, 6678). It does say that SYSCLK7 drives "slow peripherals", but where does it say that SPI belongs to "slow peripherals"? Do you see my point? TI needs to totally rethink how it does documentation. The problem is that if we screw up the design and need to respin the board (there is nothing I can mod on a bga package), there will be 3 month impact on the schedule. I can not afford that, so I need TI help and E2E is not a good way of doing it. E2E is for student question not for a company doing multi-million dollar project. Talking to a live person is appropriate way of supporting a customer.

    In the other tread I posted, I am still waiting on the GPIO boot configuration answers and I need that answered asap.

    Thank you.

    Gasha

     

     

     

     

  • 0 in reply to Slobodan Gataric
    TI__Mastermind 30825 points

    With 100MHz input Clock the SPI Clock should be SYSCLK7 (CPU/6) in Bypass mode it will work.

    If you look at the SPI section of the Data Manual, you'll see that the clocking timing is based off of SYSCLK7.

  • 0 in reply to Chad Courtney
    Expert 1020 points

    I found that little footnote at the bottom of Table 7-70 that says P2 = 1/SYSCLK7. Wow. I thought that would be in the first paragraph od chapter "7.13 SPI Peripheral" because that is pretty important information to be in a footnote.

    Thank you.

    Gasha