OMAP-L138 - 32 bit writes

Hi Dan,

Thanks for your post.

From my knowledge, EMIFA holds only 8-bit or 16-bit data bus width for all asynchronous devics (Flash, ASRAM), but you have 16-bit and 32-bit databus support for SDRAM devices.  Please refer Table 29 in SDCR of OMAPL1x EMIFA user guide below to check for narrow mode bit. This bit defines the width of the data bus between the EMIFA and the attached SDRAM device. When set to 1, the data bus is set to 16-bits. When set to 0, the data bus is set to 32-bits.

For Asynchronous devices, please refer ASIZE field in asynchronous configuration register (CEnCFG) to determine the data bus width in Table 15 in OMAPL1x EMIFA user guide as below:

http://www.ti.com/lit/ug/sprufl6f/sprufl6f.pdf

• ASIZE = 0 selects an 8-bit bus
• ASIZE = 1 selects a 16-bit bus

In the above doc, the configuration of ASIZE determines the number of external accesses required to fulfill a request from multiple sources (CPU, EDMA, master peripherals etc). For example, a request for a 32-bit word would require four external access when ASIZE = 0 and two external access when ASIZE =1. Please refer OMAPL138 TRM of Asynchronous n Configuration Registers (CE2CFG-CE5CFG) to determine the appropriate setting for this field.

TRM: http://www.ti.com/lit/ug/spruh77a/spruh77a.pdf (refer section 20.4.5)

Thanks & regards,

Sivaraj K

This doesn’t answer my question… I don’t need to know HOW to hook up the external peripheral from the chip-select perspective… I need to know what happens when the ARM software THINKS it is accessing a 32-bit register across the 16-bit external bus.  From the software’s perspective, is the “32-bit access” atomic?  By that, I mean do both 16-bit accesses happen without interruption, or could the 32-bit access be interrupted in the middle of the two 16-bit accesses?

Dan,

Looking into your question.  Haven't gotten a definitive answer yet. 

Regards.

Hi Dan

Please see if the following post helps

http://e2e.ti.com/support/dsp/omap_applications_processors/f/42/t/255786.aspx

The answer from Lo (April 09) should provide some clarifications. I expect that 32 bit accesses to EMIFA to be atomic, but bursts or higher not to be atomic.

I am going to ask some additoinal software folks from the apps team to qc my resposne, to ensure I am not missing any ARM9 features or access patterns etc.

Regards

Mukul

That's the right concern. ARM9 read/ writes  should be atomic, EXCEPT if the 32-bit int value is stored on a non-aligned address because ARM9 is byte-addressable.