AINTC documentation

Flamingo

Other Parts Discussed in Thread: OMAP-L137, AM1808

I noticed that the technical reference document (rev b, dec 2008) for the OMAP-L137 shows documentation for the AINTC memory map for ECR[0]-ECR[3] with 16 bytes, but documents only ECR[1] through ECR[3]. Making me more curious is the fact that ESR[0]-ESR[3] is documented with only 12 bytes. Again the documentation is for only 3 registers.

Am I to assume that ECR1 is at 0xfffee300? or is it at 0xfffee304?

over 16 years ago

0 Mariana over 15 years ago

TI__Mastermind 24340 points

Hi Flamingo,

Please see page 201 of the document:

OMAP-L137 Applications Processor System Reference Guide

http://www-s.ti.com/sc/techlit/SPRUG84

And also see page 73 of the datasheet:

http://www.ti.com/lit/gpn/omap-l137

So offset 0 in the first document is 0xFFFE E000 in the memory map (see datasheet).

ECR1 is at 0xFFFEE380

0 liang lee over 15 years ago

Prodigy 50 points

Hi Mariana,

Is there any example code using the ARM interrupts without Linux? I need to implement interrupts on "bare" omap-l137

0 Mariana over 15 years ago in reply to liang lee

TI__Mastermind 24340 points

Not really. Our software offering for the ARM is Linux dependent.

0 Kevin Halloran over 15 years ago in reply to liang lee

Expert 1345 points

Earlier in the year I did a port of the ARM side of OMAP-L137 to FreeRTOS and was posted to SourceForge. The source will show you how to implement interrupts using the AINTC on a "bare" omap-l137. Includes full startup code, assembler, etc...

Link is in below thread. Do a search and you will find other discussions:

https://community.ti.com/forums/p/2031/14396.aspx#14396

Kev

0 liang lee over 15 years ago in reply to Kevin Halloran

Prodigy 50 points

Thank you very much ! I'll try it

0 Anonymous over 14 years ago in reply to Kevin Halloran

Kev,

I came into this post when searching "AM1808 interrupt", and although the two processors are not identical, OMAP L137 code would still be helpful to AM1808 application.

I followed your link but it has become invalid. Could you still find the original link, or could you provide the "bare" code example again?

Zheng

0 Anonymous over 14 years ago in reply to Mariana

Mariana,

I have no experience with Linux before and am now under tight time pressure to develop a product. My purpose was to migrate my previous code on other platform to AM18x, and using "bare mode" configuration would be the most realistic choice.

Is there any code example for "bare" mode interrupt configuration on AM1x processor now?

Zheng

0 Kevin Halloran over 14 years ago in reply to Anonymous

Expert 1345 points

Hi Zheng,

I placed a zip file of the project on my company's ftp site. Should give you everything you need.

ftp://ftp.ctc-control.com/FreeRTOS/

username: support@ctc-control.com

password: ControlTech

Kev

0 Anonymous over 14 years ago in reply to Kevin Halloran

Kevin,

I have downloaded the file and will study it. Thanks very much for sharing it.

Zheng

Processors

Processors forum

AINTC documentation