Other Parts Discussed in Thread: OMAP3530
Hello all;
Be forewarned: this post will be somewhat lengthy ... read at your own risk! :)
As I'm preparing to descend into The Dungeon (our chip-testing lab here at school),
I'm wondering what I can (*try*) to do 'for fun' while designing/debugging my chip-testing
setup/board/code ...
Having successfully built a few microcontroller boards, I was looking for something more interesting
that would let me learn/study things that I don't have much knowledge about. It doesn't really have to
be 'easy', heck, it doesn't even need to work (well) eventually: I mean, who in his right mind, expects grad-student
designs to work ... well ... right? ;)
So, I figured that an attempt to build multiple-processor system might be worth a shot ... And omap (3530 in particular)
would be a good choice ... it's a nice little machine, with sufficient power, yet not really powerhungry (or so it seems), so
it would fit into all this hype about 'backing off' on the power efficiency / performance curve in computing ... going with
more cores each one being less powerful ... and so on ... and since I have no intention to code up a whole uP on my own,
this off-the-shelf component approach seems good ... and reasonably cheap that I can afford failure.
Thus, for the sake of the argument, let's 'invent' some 'intuitive' guidelines/specs for this:
>> We (I) want to build a multi-processor board. Let's say it should be capable to solve some PDEs or something like that,
a standard multiprocessor application scenario ...
>> It should be 'scalable' through message passing between boards ... which could be achieved through network connectivity
on the board. However:
>> Each board should be a shared memory system for performance. Say 2 - 4 omap3530 processors with a shared DRAM/SRAM.
Now my question would be: did anyone entertain such a thought? Maybe someone tried?
Right now, I don't see a really easy way to achieve memory sharing with all the necessary primitives, but then again I've been
looking into omap3530 datasheets for about 3 weeks now ... not all that long ...
It seems that asyncSRAM would be one way to try to achieve something along these lines ... since handshaking has to be
done anyways, so negotiation would be somewhat possible. However, this is still vague in my head, and I do not see a straightforward
way to implement it with 3530. An obvious 'complication' would be to introduce an FPGA to act as a memory controller but i would not
be very eager to do that ... unless really necessary. Other possibility is to have one of the omaps control the memory and others access it
through the 'master' device ... which is ugly from the programming perspective as I'd like to keep it symmetric.
Maybe someone knows a multi-port memory that would fit this 'off-the-shelf'? My searches were in vain: there are some two-port memories
that I found (Cypress, ... ) but the density is just laughable ... it's more of a FIFO for audio ADC interfacing than anything worth considering
for this purpose ... I'd like to have about 256MB of POP memory on each processor and ~512MB of the shared memory between processors (am I
right in assuming that a processor can have both POP and 'outside' memory ... from what I saw in datashees nothing really contradicts this, or?).
If not with 3530, does someone have an advice for a better suited processor?
Thanks for your time and reading!
/rasha