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multiple different asynchronous devices connected to EMIFA

Tobyn VanVeghten
Intellectual 700 points

Other Parts Discussed in Thread: TMS320C6748

Hey,

 

I have an application with (5) external microprocessors that can act like asynchronous FIFOs (similar to Figure 18-9 in the TMS320C6748 DSP technical reference manual).  These microprocessors have a chip select, 8-bit data bus, read, and write control lines.  I also want to connect a regular asynchronous SRAM to the C6748 (Figure 18-8 a or b).  Reading through the technical reference manual, I should be able to connect either kind of device to the C6748.  Can I connect both kinds of devices to the C6748 at the same time?  Can the DMA read from the FIFO and then write to the ASRAM?  I've seen forum posts mentioning using CE space to configure ROMs, SRAMs, etc. at the same time, but I haven't found reference to CE spaces in this particular device.

 

Thanks,

Tobyn

  • 0
    TI__Mastermind 35645 points

    Hi Tobyn,

    Thanks for your post.

    Basically, EMIFA interface would be most commonly used to interface with flash devices (NAND, NOR) and SRAM and there are also some example configuration for the EMIFA to interface with asynchronous devices. You shall use the available chipselects EMA_CS [5:2] to interface for asynchronous devices. In the TRM, you would not be able to find the example configuration for the EMIFA to interface with high speed asynchronous FIFO's but you can able to connect the same to C6748 using the chipselects available.

    CE3CFG space configuration register and chipselect space EMA_CS[3] is generally used for ASRAM asynchronous device, Likewise, CE2CFG configuration register and chipselect space EMA_CS[2] is used for NAND flash device. So, you shall use the remaining chipselect space EMA_CS[4,5] to configure EMIFA to interface with high speed FIFO devices. In general, there are EMIFA and asynchronous device (ASRAM, NAND flash etc) timing requirements needs to be met while configuring the appropriate device with EMIFA.

    Please find the available example configuration for the EMIFA to interface with ASRAM & NAND flash device in the C6748 TRM as below:

    http://www.ti.com/lit/ug/spruh79a/spruh79a.pdf (Refer Sections 18.3.2.2. & 18.3.2.3 in the TRM)

    Thanks & regards,

    Sivaraj K

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  • 0
    TI__Guru* 84110 points

    Tobyn,

    Have you solved your design problem using the information Sivaraj provided? If so, please mark his post with Verified Answer so we will know this has been resolved.

    If not, please let us know what additional information you need.

    Since all 5 microprocessor interfaces will have similar timing, you might be able to use on of the four (4) CEn pins for all 5 microprocessors. This will require additional decoding to distinguish between the 5 different FIFO interfaces, but perhaps this can be done with one address line dedicated to each of the 5 microprocessors. This may require a small CPLD or some logic gates, but could be designed without too much difficulty.

    The ASRAM can then be connected to one of the other three CEn pins and can have its own timing parameters.

    The DMA can read from a FIFO and then write to the ASRAM. It would simply be a copy from one memory address to another, and that is not an issue.

    Regards,
    RandyP