SDRAM Problem when interface to OMAP-L137 (Need help)

hua chen16481

Other Parts Discussed in Thread: OMAP-L137

Hello,

I am experiencing an problem with my SDRAM. I have a single OMAP-L137 processor attached to two Micron MT48LC16M16A2-75:D, 16-bits SDRAM chips. The chips are arranged to function as a single 32-bit device. They are attached via EMIFB_CS0n. The OMAP-L137 is run at 300Mhz, and SDRAM run at 100Mhz, and I use the spetrum's dsp test code, just modify the SDRAM CL to 3, but the sdram works very bizarre.

1) when write a sequent data like 0,1,2,3,4,5,....................., then read from sdram and storge data at DSP L2 ram, the data is rambling, only some address is right.

2) Change the sdram clk from 100Mhz to 10Mhz, the situation is same.

3) when write the same data 1000time, then read also 1000 time, the data is right.

I am very struggling with this problem, I have probe the signal, the signal seems right. I do not know the root cause.

over 15 years ago

0 Brad Griffis over 15 years ago

TI__Guru*** 125430 points

Sounds like your timings are wrong. Recalculate your register settings based on the example in Appendix A of sprufl6.

Also, you need to pick your EMIF clock frequency and stick to it. Simply trying to slow it down is not effective for this interface since all your timings will change relative to your new EMIF clock frequency. I assume you were not recalculating all your register settings when you slowed it down.

0 hua chen16481 over 15 years ago in reply to Brad Griffis

Prodigy 60 points

Hi brad,

Thank you for your reply.

As your suggestion, I have tried two emifb sdram parameters:

1)133Mhz

//    // Micron MT48LC16M16A2P-75D SDRAM, 2 x 16M x 16 (32-bit data path), 133MHz
//    // Compatible with HY57V561620
//    EMIFB_SDCFG |= 0x00800000; // Set BOOT_UNLOCK to 1
//    EMIFB_SDCFG |= 0x00010000; //Set SDREN to 1
//    EMIFB_SDCFG |= 0x00008000; //Set TIMUNLOCK to 1
//    EMIFB_SDTIM1 = 0        // SDRAM Timing Register 1
//        |( 8 << 25)        // (67.5 / 7.5ns) - 1 = TRFC @ 133MHz
//        |( 2 << 22 )        // (20ns / 7.5ns) - 1 =TRP
//        |( 2 << 19 )        // (20ns / 7.5ns) - 1 = TRCD
//        |( 1 << 16 )        // (14ns / 7.5ns) - 1 = TWR
//        |( 5 << 11 )        // (45ns / 7.5ns) - 1 = TRAS
//        |( 8 << 6 )        // (67.5ns / 7.5ns) - 1 = TRC
//        |( 1 << 3 );       // 15/7.5 = TRRD
//    EMIFB_SDTIM2 = 0        // SDRAM Timing Register 2
//        |( 14<< 27)         //TRASMAX is 120k.
//        |( 1 << 16)         // T_SRE
//        |( 1 << 0 );        // T_CKE ( 45 / 7.5 ) - 1
// EMIFB_SDREF = 0         // SDRAM Refresh Control Register
//        |( 0 << 31)         // Low power mode disabled
//        |( 0 << 30)         // MCLK stoping disabled
//        |( 0 << 23)         // Selects self refresh instead of power down
//        |( 1040 <<0);       // Refresh rate = 133Mhz*64ms/8192
//    EMIFB_SDCFG = 0         // SDRAM Bank Config Register
//          |( 0 << 26)         // IBANK_POS   0-sdr sdram 1-mb sdram
//          |( 0 << 25)         // MSDRAM_ENABLE
//          |( 0 << 23)         // BOOT_UNLOCK
//          |( 1 << 16)         // SDREN
//        |( 0 << 15)         // Unlock timing registers
//        |( 0 << 14)         // NM 0-32bit 1-16bit
//        |( 3 << 9 )         // CAS latency is 3
//        |( 2 << 4 )         // 4 bank SDRAM devices
//        |( 0 << 3 )         // EBANK
//        |( 1 << 0 );        // 512-word pages requiring 9 column address bits
//}

2)50Mhz

    EMIFB_SDCFG |= 0x00800000; // Set BOOT_UNLOCK to 1
    EMIFB_SDCFG |= 0x00010000; //Set SDREN to 1
    EMIFB_SDCFG |= 0x00008000; //Set TIMUNLOCK to 1
    EMIFB_SDTIM1 = 0        // SDRAM Timing Register 1
        |( 3 << 25)        // (67.5 / 20ns) - 1 = TRFC @ 50MHz
        |( 0 << 22 )        // (20ns / 20ns) - 1 =TRP
        |( 0 << 19 )        // (20ns / 20ns) - 1 = TRCD
        |( 0 << 16 )        // (14ns / 20ns) - 1 = TWR
        |( 2 << 11 )        // (45ns / 20ns) - 1 = TRAS
        |( 8 << 6 )        // (67.5ns / 20ns) - 1 = TRC
        |( 0 << 3 );       // 15/20 = TRRD
    EMIFB_SDTIM2 = 0        // SDRAM Timing Register 2
        |( 14<< 27)         //TRASMAX is 120k.
        |( 1 << 16)         // T_SRE
        |( 1 << 0 );        // T_CKE ( 45 / 7.5 ) - 1
EMIFB_SDREF = 0         // SDRAM Refresh Control Register
        |( 0 << 31)         // Low power mode disabled
        |( 0 << 30)         // MCLK stoping disabled
        |( 0 << 23)         // Selects self refresh instead of power down
        |( 390 <<0);       // Refresh rate = 133Mhz*64ms/8192
    EMIFB_SDCFG = 0         // SDRAM Bank Config Register
          |( 0 << 26)         // IBANK_POS   0-sdr sdram 1-mb sdram
          |( 0 << 25)         // MSDRAM_ENABLE
          |( 0 << 23)         // BOOT_UNLOCK
          |( 1 << 16)         // SDREN
        |( 0 << 15)         // Unlock timing registers
        |( 0 << 14)         // NM 0-32bit 1-16bit
        |( 3 << 9 )         // CAS latency is 3
        |( 2 << 4 )         // 4 bank SDRAM devices
        |( 0 << 3 )         // EBANK
        |( 1 << 0 );        // 512-word pages requiring 9 column address bits
}

0 hua chen16481 over 15 years ago in reply to hua chen16481

Prodigy 60 points

My test code is as blew:

for(j=0;j<1;j++)
for(i=0;i<Length;i++)
    {
        *(SDRAM_StartAdd+i) = (i<<16);
    }

for(j=0;j<1;j++)
for(i=0;i<Length;i++)
{
    inter_data[i] = *(SDRAM_StartAdd+i);
}

and the result is that:

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SDRAM Problem when interface to OMAP-L137 (Need help)