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PCIe clock requirements for C66x DSP

Anfernee Chang
Intellectual 1015 points

Hi Champs,

 

According to the design guide and user guide, the PCIECLK input clock requirements is more precise than the PCI Express Card Electromechanical Specification (eg. duty cycle 45/55 vs. 40/60).

Is it acceptable for the case that input clock confirmed to meet the spec from backplane? Or it's must to follow TI design guide requirement?

 

Regards,

Anfernee 

  • 0
    TI__Mastermind 42545 points

    Hi Anfernee,

    The design guide provides the a PCIECLK requirement at the level of detail that we use for specifying all serdes reference clocks. The design team felt that the clock spec in the PCI Express Electromechanical specification was incomplete in some regards but they tested the serdes using a clock with those specifications and verified that the device would operate correctly with a backplane clock. If the customer is not using a backplane clock we expect them to meet the clock requirements specified in the hardware design guide.

    Regards, Bill