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Read operation from EMIFB on C6747

Naoki Kawada
Guru 19890 points

Hi,

Just a quick question.
16bit width SDRAM is connected to EMIFB.
When DSP core/EDMA3 reads a 32bit data from EMIFB(SDRAM), two 16bit reads will occur.
So my question is, witch 16bit word will come first, lower or higher ?
I believe lower 16bit data should always come first. Is my understanding correct ?

Best Regards,
Kawada 

  • 0
    TI__Mastermind 35645 points

    Hi Kawada,

    Thanks for your post.

    It usually drives the lower 16-bit word first (from LSB) and later the next (higher) 16-bit data. For more information on this, please refer the OMAPL1x EMIF user guide as below:

    http://www.ti.com/lit/ug/sprufl6f/sprufl6f.pdf

    Thanks & regards,

    Sivaraj K

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  • 0 in reply to Sivaraj Kuppuraj
    Guru 19890 points

    Hi Sivaraj,

    Thank you for your reply.
    I understood my assumption was correct.
    I checked the document and found that it was for EMIFA, not for EMIFB.
    I believe the logic for SDRAM is same between EMIFA and EMIFB, but as you know, I'm asking about EMIFB.
    Could you guide me the descriptions in the document ? I briefly checked, but I could not find the related explanation.

    Best Regards,
    Kawada
     

  • 0 in reply to Naoki Kawada
    Guru 19890 points

    If lower 16bit first is always expected by *EMIFB design*, it is ok for me even if it is not described in the document.
    (but it would be helpful if documented)
    Now I need to have TI's answer whether lower 16bit first is always expected in *EMIFB design* point of view.
    If lower 16bit first is expected by design, I can close this thread.

    Best Regards,
    Kawada 

  • 0 in reply to Naoki Kawada
    TI__Intellectual 1780 points

    Hi,

    I did simple read back test with DMA transfer with 16but bus configuration on EMIFB.

    Condition:

      SRC[0] = 0xaaaa5555; (located in 0xC8000000)
      SRC[1]= 0x5555aaaa; (located in 0xC8000004)
      SRC[2]= 0xFFFFFFFF; (located in 0xC8000008)
      SRC[3]= 0x00000000; (located in 0xC800000C)

       DST was located in 0x80000000 (L3 RAM)

    When I execute ACNT = 0x10, I could get below figure::

    Lower 16bit of first word is 0x5555, then D[0] = high, and D[1] = low, and upper 16bit of first word is 0xAAAA, then next cycle,  D[0] = low, and D[1] = high.

    That could lead the the order of C6747 EMIFB 16bit SDRAM read is lower -> upper,I think.

    best regaeds,

    Hirofumi Fujita  

     

  • 0 in reply to Hirofumi Fujita
    Guru 19890 points

    Hi Fujita-san,

    Thank you for your experiment! This can help to promote that lower 16bit is expected first. To verify it is ALWAYS expected, I need to clarify EMIFB never changes the order of read sequence.

    Best Regards,
    Kawada