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GPIO interrupt problem

Hello, my question is about csl example with gpio interrupt.

void main (
void
)
{

Next 3 operations are not completed  successfully in debugger , because operation is in endless loop with    gpioEn != TRUE 

Bool gpioEn;

/* Unlock the control register */
CSL_FINST(((CSL_DevRegs*)CSL_DEV_REGS)->PERLOCK, DEV_PERLOCK_LOCKVAL, UNLOCK);

/* Enable the GPIO */
CSL_FINST(((CSL_DevRegs*)CSL_DEV_REGS)->PERCFG0, DEV_PERCFG0_GPIOCTL, ENABLE);

do {
gpioEn = (Bool) CSL_FEXT(((CSL_DevRegs*)CSL_DEV_REGS)->PERSTAT0, DEV_PERSTAT0_GPIOSTAT);
} while (gpioEn != TRUE);

/* Invoking example script */
gpioInternalLoopbackDemo();

  return;
}

  if I will comment thus 3 operations, program will be in other endless loop, tells that interrupt was not generated   

void gpioInternalLoopbackDemo (
void
)
{
CSL_Status intStat;
CSL_GpioPinConfig config;
CSL_GpioPinNum pinNum;
CSL_Status status;
CSL_GpioContext pContext;
CSL_GpioObj gpioObj;
CSL_GpioHwSetup hwSetup;
CSL_IntcGlobalEnableState state;
CSL_IntcParam vectId;


/* Initialize INTC */
context.numEvtEntries = 1;
context.eventhandlerRecord = record;

intStat = CSL_intcInit(&context);

/* Enable NMIs */
intStat = CSL_intcGlobalNmiEnable();

/* Enable all interrupts */
intStat = CSL_intcGlobalEnable(&state);

/* Open interrupt module */
vectId = CSL_INTC_VECTID_12;

gpioIntcHandle = CSL_intcOpen(&gpioIntcObj, CSL_INTC_EVENTID_GPINT5,&vectId, &intStat);

/* Bind ISR to Interrupt */
isr_gpio.handler = (CSL_IntcEventHandler)&HandleGPIO_INT;
isr_gpio.arg = gpioIntcHandle;
CSL_intcPlugEventHandler(gpioIntcHandle, &isr_gpio);

/* Event Enable */
CSL_intcHwControl(gpioIntcHandle, CSL_INTC_CMD_EVTENABLE, NULL);

/* Initialize the GPIO CSL module */
status = CSL_gpioInit(&pContext);

/* Open the CSL module */
hGpio = CSL_gpioOpen(&gpioObj, CSL_GPIO, NULL, &status);

intrCnt = 0;

/* Setup hardware parameters */
hwSetup.extendSetup = NULL;

/* Setup the General Purpose IO */
status = CSL_gpioHwSetup(hGpio, &hwSetup);

/* Configure pin 5 to generate an interrupt on Rising Edge, and
* configure it as an output, then set the data High (Low->High).
* Set Trigger:
*/
config.pinNum = CSL_GPIO_PIN5;
config.trigger = CSL_GPIO_TRIG_RISING_EDGE;
config.direction = CSL_GPIO_DIR_OUTPUT;

/* Enable the bank interrupt */
status = CSL_gpioHwControl(hGpio, CSL_GPIO_CMD_BANK_INT_ENABLE, NULL);

/* configure the gpio pin 5 */
status = CSL_gpioHwControl(hGpio, CSL_GPIO_CMD_CONFIG_BIT, &config);

/* Set Data High: */
pinNum = CSL_GPIO_PIN5;
status = CSL_gpioHwControl (hGpio, CSL_GPIO_CMD_SET_BIT, &pinNum);

/* Wait for interrupt to be generated. */
while (1) {
if (intrCnt == 1)
break;
}

/* Set Data Low again: */
pinNum = CSL_GPIO_PIN5;
status = CSL_gpioHwControl(hGpio, CSL_GPIO_CMD_CLEAR_BIT, &pinNum);

status = CSL_gpioClose(hGpio);

return;
}

  • Hi Igor,

    Thanks for your post.

    Could you please make sure whether the polarity of the interrupt is configured properly using gppol register for the rising edge trigger on the corresponding GPIO port?

    Also, could you please check the GPIO module register like GPDH for the transition direction that triggers an interrupt which is selected properly or not?

    Please find the below wiki for the GPIO interrrupt controller configuration and also an example project for GPIO interrupts is given on the same wiki:

    http://processors.wiki.ti.com/index.php/Configuring_GPIO_Interrupts#Example_Project

    If you need to validate CSL package for all C64x+ devices, please refer the below wiki:

    http://processors.wiki.ti.com/index.php/Chip_support_library#C64x.2B_Devices

    Thanks & regards,

    Sivaraj K

    -------------------------------------------------------------------------------------------------------
    Please click the Verify Answer button on this post if it answers your question.
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  • Hi Sivaraj, thanks for your wish help.

    I think that gpio is configured correctly . In picture below is shown Gpio regs after manually gpio set. There is no GPDH register in DSP 6455

    To let process to run gpioInternalLoopbackDemo() i commened first loop

    // do {
    gpioEn = (Bool) CSL_FEXT(((CSL_DevRegs*)CSL_DEV_REGS)->PERSTAT0, DEV_PERSTAT0_GPIOSTAT);
    // } while (gpioEn != TRUE);

     And in picture below core registers. 

  • I had found that GPIO module doesn't included in CCS v5 simulator. It simulates the 64+ core. Megamodule(L1P Progrm Cache, L1D Data Cache, L2 Unified mapped RAM/Cache, L2 ROM), SCR, EDMA3CC, EDMANC(0-3), Timers(2), EMIFA, EMIFB, TCP, VCP, McBSP and external memory. How can I model GPIO interrupt in simulator?